• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.107-116
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• 2012

In this paper, the trade-off related to bandwidth of high-speed common-mode logic frequency divider is analyzed in detail. A method to optimize the operating frequency, band-width as well as power consumption is proposed. This method is based on bipolar device characteristics, whereby a negative resistance model can be used to estimate the optimal normalized upper frequency and lower frequency of frequency dividers under different conditions, which is conventionally ignored in literatures. This method provides a simple but efficient procedure in designing high performance frequency dividers for different applications. To verify the proposed method, a static divide-by-2 at millimeter wave ranges is implemented in 180 nm SiGe technology. Measurement results of the divider demonstrate significant improvement in the figure of merit as compared with literatures.

• Journal of the Korea Safety Management & Science
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• v.10 no.2
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• pp.95-103
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• 2008

The package loading process of the lumbering industry is an operation that after a pair of workers bind three or six lumbers into one unit and cut both ends of the lumbers, transports the weight cargo of 30-50kg by one meter, pack and load at a height of 1.2 meters. This package loading process causes lots of noise and wood dust when workers carry out the heavy work as the above. Therefore we developed the monolithic both ends cutting package loading equipment in order to prevent from getting musculoskeletal disease. An loading bar working system of this equipment is improved from pneumatic pressure system to oil pressure system, furnished the newly designed flow dividers, and developed the new system that a both end array is loaded identically. Also we developed the safety equipment of loading bar in order to prevent workers mistake and overload from malfunction during the package loading process. The main cause of job evasion on working place could be solved by preventing the musculoskeletal disease and improving the working environments.

• Proceedings of the Safety Management and Science Conference
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• 2008.04a
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• pp.135-147
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• 2008

The package loading process of the lumbering industry is an operation that after a pair of workers bind three or six lumbers into one unit and cut both ends of the lumbers, transports the weight cargo of 30-50kg by one meter, pack and load at a height of 1.2 meters. This package loading process causes lots of noise and wood dust when workers carry out the heavy work as the above. Therefore we developed the monolithic both ends cutting package loading equipment in order to prevent from getting musculoskeletal disease. An loading bar working system of this equipment is improved from pneumatic pressure system to oil pressure system, furnished the newly designed flow dividers, and developed the new system that a both end array is loaded identically. Also we developed the safety equipment of loading bar in order to prevent workers mistake and overload from malfunction during the package loading process. The main cause of job evasion on working place could be solved by preventing the musculoskeletal disease and improving the working environments.

• Journal of Biosystems Engineering
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• v.41 no.4
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• pp.408-417
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• 2016

Purpose: Yield monitoring systems are an essential component of precision agriculture. They indicate the spatial variability of crop yield in fields, and have become an important factor in modern harvesters. The objective of this paper was to review research trends related to yield monitoring sensors for grain crops. Methods: The literature was reviewed for research on the major sensing components of grain yield monitoring systems. These major components included grain flow sensors, moisture content sensors, and cutting width sensors. Sensors were classified by sensing principle and type, and their performance was also reviewed. Results: The main targeted harvesting grain crops were rice, wheat, corn, barley, and grain sorghum. Grain flow sensors were classified into mass flow and volume flow methods. Mass flow sensors were mounted primarily at the clean grain elevator head or under the grain tank, and volume flow sensors were mounted at the head or in the middle of the elevator. Mass flow methods used weighing, force impact, and radiometric approaches, some of which resulted in measurement error levels lower than 5% ($R^2=0.99$). Volume flow methods included paddle wheel type and optical type, and in the best cases produced error levels lower than 3%. Grain moisture content sensing was in many cases achieved using capacitive modules. In some cases, errors were lower than 1%. Cutting width was measured by ultrasonic distance sensors mounted at both sides of the header dividers, and the errors were in some cases lower than 5%. Conclusions: The design and fabrication of an integrated yield monitoring system for a target crop would be affected by the selection of a sensing approach, as well as the layout and mounting of the sensors. For accurate estimation of yield, signal processing and correction measures should be also implemented.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.12C
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• pp.1288-1298
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• 2002

To implement elliptic curve cryptosystem in GF(2$\^$m/) at high speed, a fast divider is required. Although bit-parallel architecture is well suited for high speed division operations, elliptic curve cryptosystem requires large m(at least 163) to support a sufficient security. In other words, since the bit-parallel architecture has an area complexity of 0(m$\^$m/), it is not suited for this application. In this paper, we propose a new serial-in serial-out systolic array for computing division operations in GF(2$\^$m/) using the standard basis representation. Based on a modified version of tile binary extended greatest common divisor algorithm, we obtain a new data dependence graph and design an efficient bit-serial systolic divider. The proposed divider has 0(m) time complexity and 0(m) area complexity. If input data come in continuously, the proposed divider can produce division results at a rate of one per m clock cycles, after an initial delay of 5m-2 cycles. Analysis shows that the proposed divider provides a significant reduction in both chip area and computational delay time compared to previously proposed systolic dividers with the same I/O format. Since the proposed divider can perform division operations at high speed with the reduced chip area, it is well suited for division circuit of elliptic curve cryptosystem. Furthermore, since the proposed architecture does not restrict the choice of irreducible polynomial, and has a unidirectional data flow and regularity, it provides a high flexibility and scalability with respect to the field size m.