• Journal of the Optical Society of Korea
• /
• v.18 no.6
• /
• pp.706-713
• /
• 2014

An enhanced 360-degree integral-floating three-dimensional display system using a hexagonal lens array and a hidden point removal operator is proposed. Only the visible points of the chosen three-dimensional point cloud model are detected by the hidden point removal operator for each rotating step of the anamorphic optics system, and elemental image arrays are generated for the detected visible points from the corresponding viewpoint. Each elemental image of the elemental image array is generated by a hexagonal grid, due to being captured through a hexagonal lens array. The hidden point removal operator eliminates the overlap problem of points in front and behind, and the hexagonal lens array captures the elemental image arrays with more accurate approximation, so in the end the quality of the displayed image is improved. In an experiment, an anamorphic-optics-system-based 360-degree integral-floating display with improved image quality is demonstrated.

• Journal of Ocean Engineering and Technology
• /
• v.12 no.2 s.28
• /
• pp.121-129
• /
• 1998

A quantitative non-contact multi-point measurement system is proposed to the measurement of three-dimensional movement of floating vessels by using digital image processing. The instantaneous three-dimensional movement of a floating structure which is floating in a small water tank is measured by this system and its three-dimensional movement is reconstructed by the measurement results. The validity of this system is verified by position identification for spatially distributed known positional values of basic landmarks set for the camera calibration. It is expected that this system is applicable to the non-contact measurement for an unsteady physical phenomenon especially for the measurement of three-dimensional movement of floating vessels in the laboratory model test.

• The KIPS Transactions:PartA
• /
• v.13A no.3 s.100
• /
• pp.185-190
• /
• 2006

JPEG 2000 is used as an alternative to solve the blocking artifact problem with the existing still image compression JPEG algorithm. However, it has shortcomings such as longer floating point computation time and more complexity in the procedure of enhancing the image compression rate and decompression rate. To compensate for these we implemented with hardware the JPEG 2000 algorithm's filter part which requires a lot of floating point computation. This DWT Filter[1] chip is designed on the basis of Daubechies 9/7 filter[6] and is composed of 3-stage pipeline system to optimize the performance and chip size. Our implemented Filter was 7 times faster than software based Filter in the floating point computation.

• Journal of IKEEE
• /
• v.26 no.2
• /
• pp.240-248
• /
• 2022

Floating-point images that express pixel information as real numbers are used in HDR images. There have been various researches on efficient median filter algorithms, but most of them are applicable to 8-bit depth images and there are only a few number of algorithms applicable to floating-point images, including Gil and Werman's algorithm. In this paper, we propose a median filter algorithm that works efficiently on floating-point images by improving Kim's algorithm, which improved Gil and Werman's algorithm. Experimental results show that the execution time is improved by about 10% compared to the Kim's algorithm by reducing the redundant work for the repetitively used binary search tree and applying the inverted index.

• The KIPS Transactions:PartB
• /
• v.13B no.4 s.107
• /
• pp.429-438
• /
• 2006

Neural Networks(NNs) are applied for solving a wide variety of nonlinear problems in several areas, such as image processing, pattern recognition etc. Although NN can be simulated by using software, many potential NN applications required real-time processing. Thus they need to be implemented as hardware. The hardware implementation of multi-layer perceptrons(MLPs) in several kind of NNs usually uses a fixed-point arithmetic due to a simple logic operation and a shorter processing time compared to the floating-point arithmetic. However, the fixed-point arithmetic-based MLP has a drawback which is not able to apply the MLP software that use floating-point arithmetic. We propose a design method for MLPs which has the floating-point arithmetic-based fully-pipelining architecture. It has a processing speed that is proportional to the number of the hidden nodes. The number of input and output nodes of MLPs are generally constrained by given problems, but the number of hidden nodes can be optimized by user experiences. Thus our design method is using optimized number of hidden nodes in order to improve the processing speed, especially in field of a repeated processing such as image processing, pattern recognition, etc.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.11 no.1
• /
• pp.175-181
• /
• 2010

In this paper, we propose a novel hardware architecture for Rate control module for real time full HD video compression. In the proposed architecture, QP is updated by using the rate control algorithm to every the macroblock line(120MB for Full HD, 20MB for CIF image). Since there are many complex arithmetic and floating point arithmetic in rate control algorithm of JM for H.264, it is impossible to process the rate control algorithm using the integer arithmetic CPU core. So we adopted floating point arithmetic unit in our architecture, and implemented the rate control algorithm using the floating unit. With this implemented hardware, the implemented hardware is verified to be operated in real time.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.2
• /
• pp.102-113
• /
• 2014

This paper suggests a novel hardware architecture of a real-time rectification which is to remove vertical parallax of an image occurred in the pre-processing stage of stereo matching. As an off-line step, Matlab Toolbox which was designed by J.Y Bouguet, was used to calculate calibration parameter of the image. Then, based on the Heikkila and Silven's algorithm, rectification hardware was designed. At this point, to enhance the precision of the rectified image, floating-point unit was generated by using Xilinx Core Generator. And, we confirmed that proposed hardware design had higher precision compared to other designs while having the ability to do rectification in real-time.

• Journal of the Korean Crystal Growth and Crystal Technology
• /
• v.4 no.3
• /
• pp.325-335
• /
• 1994

The spinel $MgO.Al_20_3$ single crystals were grown by FZ (floating zone) method. Its melting point is about, $2135^{\circ}C$ and is important to the process of the growth from the melt. There have been some reports of the growth by Czochralski and Verneuil method. However, this study is the first trial to the spinel crystal with the application of FZ method. In this study, $MgAl_2O_4$ spinel crystals were grown by using FZ method which uses the ellipsoidal mirror furnace having infrared halogen lamps as a heat source. With dopants of transition metal ions, it was possible to melt the feed rod which does not absorb the infrared rays due to the transparent properties to infrared ray of spinel itself and the red, green and blue colored spinel single crystals could be grown more easily. As a conclusion, the purpose of this study is to find the spinel single crystal growth mechanism with respect to th growth interfaces and molten zone stability and to characterize the state of growth resulting from the concavity to the melt of interfaces.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.8 no.1
• /
• pp.25-29
• /
• 2013

Recently ARM processor's processing power has been increasing rapidly as it has been applied to consumer electronics products. Because of its computing power and low power consumption, it is used to various embedded systems.( including vision processing systems.) Embedded linux that provides well-made platform and GUI is also a powerful tool for ARM based embedded systems. So short period to develop is one of major advantages to the ARM based embedded system. However, for real-time date processing applications such as an image processing system, ARM needs additional equipments such as FPGA that is suitable to parallel processing applications. In this paper, we developed an embedded system using ARM processor and FPGA. FPGA takes time consuming image preprocessing and numerical algorithms needs floating point arithmetic and user interface are implemented using the ARM processor. Overall processing speed of the system is 60 frames/sec of VGA images.

• KIPS Transactions on Software and Data Engineering
• /
• v.2 no.11
• /
• pp.809-814
• /
• 2013

Summed area table (SAT) is a data structure in which the sum of pixel values in an arbitrary rectangular area can be represented by the linear combination of four pixel values. Since SAT serially accumulates the pixel values from an image corner to the other corner, a high-resolution image can yield overflow in a floating-point representation. In this paper, we present a new SAT construction technique, which accumulates only the residuals from the linearly-regressed representation of an image and thereby significantly reduces the accumulation errors. Also, we propose a method to find the integral of the linear regression in constant time using double integral. We performed experiments on the image reconstruction, and the results showed that our approach more reduces the accumulation errors than the conventional fixed-offset SAT.