• Journal of KIISE
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• v.42 no.12
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• pp.1480-1485
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• 2015

As SSDs are increasingly being used as high-performance storage or caches, attention is increasingly paid to the provision of SSDs with Quality-of-Service for I/O request streams of various applications in server systems. Since most SSDs are using the AHCI controller interface on a SATA bus, it is not possible to provide a differentiated service by distinguishing each I/O stream from others within the SSD. However, since a new SSD interface, the NVME controller interface on a PCI Express bus, has been proposed, it is now possible to recognize each I/O stream and schedule I/O requests within the SSD for differentiated services. This paper proposes Flash Operation Group Scheduling within NVME-based flash storage devices, and demonstrates through QEMU-based simulation that we can achieve a proportional bandwidth share for each I/O stream.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.188-198
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• 2013

In order to increase its performance, NAND flash memory-based storage is composed of data buses that are shared by a number of flash memories and uses a parallel technique that can carry out multiple flash memory operations simultaneously. Since the storage performance is strongly influenced by the performance of each data bus, it is important to improve the utilization of the bus by ensuring effective scheduling of operations by the storage controller. However, this is difficult because of dynamic changes in buses due to the unique characteristics of each operation with different timing, cost, and usage by each bus. Furthermore, the scheduling technique for increasing bus utilization may cause unanticipated operation delay and wastage of storage resource. In this study, we suggest various dynamic operation scheduling techniques that consider data bus performance and storage resource efficiency. The proposed techniques divide each operation into three different stages and schedule each stage depending on the characteristics of the operation and the dynamic status of the data bus. We applied the suggested techniques to the controller and verified them on the FPGA platform, and found that program operation decreased by 1.9% in comparison to that achieved by a static scheduling technique, and bus utilization and throughput was approximately 4-7% and 4-19% higher, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.48-56
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• 2011

Recently, new storage device SSD(Solid State Disk) based on NAND flash memory is gradually replacing HDD(Hard Disk Drive) in mobile device and thus a variety of research efforts are going on to find the cost-effective ways of performance improvement. By increasing the NAND flash channels in order to enhance the bandwidth through parallel processing, DRAM buffer which acts as a buffer cache between host(PC) and NAND flash has become the bottleneck point. To resolve this problem, this paper proposes an efficient low-cost scheme to increase SSD performance by improving DRAM buffer bandwidth through scheduling techniques which utilize DRAM multi-banks. When both host and NAND flash multi-channels request access to DRAM buffer concurrently, the proposed technique checks their destination and then schedules appropriately considering properties of DRAMs. It can reduce overheads of bank active time and row latency significantly and thus optimizes DRAM buffer bandwidth utilization. The result reveals that the proposed technique improves the SSD performance by 47.4% in read and 47.7% in write operation respectively compared to conventional methods with negligible changes and increases in the hardware.