• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2004.11a
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• pp.65-69
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• 2004

The small form factor optical data storage devices are developing rapidly nowadays. Since it is designed for portable and compatibility with flash memory, its components such as disk, head, focusing actuator, and spindle motor should be assembled within 5 m thickness. The thickness of focusing actuator is within 2 mm and the total working range is $+/-100{\mu}m$, with the resolution of less than $1{\mu}m$. Since the thickness is limited tightly, it is hard to place the yoke that closes the magnetic circuit and hard to make strong flux density without yoke. Therefore, Halbach array is adopted to increase the magnetic flux of one side without yoke. The proposed Halbach array type focusing actuator has the advantage of thin actuation structure with sacrificing less flux density than conventional magnetic array. The optical head unit is moved on the swing arm type tracking actuator. Focusing coil is attached to swing arm, and Halbach magnet array is positioned at the bottom of deck along the tracking line, and focusing actuator exerts force by the Fleming's left hand rule. The working range and resolution of focusing actuator are analyzed with FEM and experiment.

• Smart Structures and Systems
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• v.6 no.5_6
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• pp.661-673
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• 2010

This paper presents recent developments in an extremely compact, wireless impedance sensor node (the WID3, $\underline{W}$ireless $\underline{I}$mpedance $\underline{D}$evice) for use in high-frequency impedance-based structural health monitoring (SHM), sensor diagnostics and validation, and low-frequency (< ~1 kHz) vibration data acquisition. The WID3 is equipped with an impedance chip that can resolve measurements up to 100 kHz, a frequency range ideal for many SHM applications. An integrated set of multiplexers allows the end user to monitor seven piezoelectric sensors from a single sensor node. The WID3 combines on-board processing using a microcontroller, data storage using flash memory, wireless communications capabilities, and a series of internal and external triggering options into a single package to realize a truly comprehensive, self-contained wireless active-sensor node for SHM applications. Furthermore, we recently extended the capability of this device by implementing low-frequency analog-to-digital and digital-to-analog converters so that the same device can measure structural vibration data. The compact sensor node collects relatively low-frequency acceleration measurements to estimate natural frequencies and operational deflection shapes, as well as relatively high-frequency impedance measurements to detect structural damage. Experimental results with application to SHM, sensor diagnostics and low-frequency vibration data acquisition are presented.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.05a
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• pp.355-357
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• 2014

Linux environment that is commonly used at embedded systems, supports various file systems as Ext2, FAT, NTFS, ets. The file system that is equiped on the embedded system is mostly implemented on mini hard disk or flash memory. The types of the file system of the system make an effect on the performance of a application programs. The factors of file system performance on a same media are block allocation and block free time. On these factors, block free time is not so different according to the type of file systems. This thesis performs the performance benchmark of a Ext2, FAT and NTFS file systems about block allocation performance. As the result, it is discussed that what file system is better at which case.

• Proceedings of the Korea Information Processing Society Conference
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• 2008.11a
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• pp.860-863
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• 2008

플래시 메모리는 우리 생활에 널리 사용되고 있는 휴대용 저장장치 중의 하나이다. 빠른 입출력 속도와 저전력, 무소음, 작은 크기 등의 장점을 가지나 덮어쓰기가 불가능하고 읽기/쓰기의 속도에 비해 소거 연산의 속도가 매우 느리다는 단점이 있다. 이를 보완하기 위해, 호스트와 플래시 메모리 사이에 버퍼 캐시를 두어 사용하고 있으며, 버퍼 캐시에 사용되는 교체 정책에 따라 플래시 메모리 장치의 성능이 크게 영향을 받는다. 본 논문에서는 블록 단위의 LRU 기법의 단점을 개선한 HPLRU 기법을 제안한다. HPLRU 기법은 최근에 자주 참조되었던 페이지인 핫 페이지 들을 모아 리스트를 만들어 관리하고, 이를 통해 페이지 적중률을 향상시키고 다른 페이지들로 인해 핫 페이지들이 소거되는 현상을 개선하였다. 이 알고리즘은 임의 데이터 패턴에 좋은 성능을 보이며 쓰기 발생 횟수를 많이 감소시키는 결과를 보였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2008.05a
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• pp.204-207
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• 2008

NAND 플래시 메모리는 하드 디스크에 비해 작고, 빠르며, 저 전력 소모 등과 같은 장점을 가지고 있어 대체 저장 매체로 주목받고 있다. 그러나 제자리 갱신이 불가능한 특징을 가지고 있어 B-트리를 사용하면 갱신이 빈번하게 발생하여 읽기 연산에 비해 상대적으로 느린 쓰기 연산과 소거 연산이 빈번해져 시스템의 성능이 저하 된다. 이러한 성능 저하를 피하기 위해 $\mu}$-트리가 제안되었으나, 고정된 페이지 레이아웃 구조를 가지고 있어 노드 분할과 트리 신장이 빈번하게 일어난다. 본 논문에서는 NAND 플래시 메모리 상에서 B-트리 구현 시 발생하는 추가적인 쓰기 연산의 횟수를 줄이기 위해 갱신이 일어나는 단말 노드에 로그 노드를 할당하여, 갱신되는 내용을 저장한다. 따라서 부모 노드의 내용이 변경 되는 것을 늦추어 추가적인 쓰기 연산을 줄이게 되며, 순차적인 키 값의 삽입이나 일정 노드에 대한 빈번한 갱신은 로그 노드가 단말 노드로 전환되어 추가적인 쓰기 연산을 줄이게 된다. 이러한 방법으로 추가적인 쓰기 연산을 줄임으로써 시스템의 성능을 향상시키는 NAND 플래시 메모리를 위한 새로운 B-트리 구조를 제안한다.

• Proceedings of the Korea Information Processing Society Conference
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• 2007.05a
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• pp.885-888
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• 2007

본 논문은 무선 센서노드에서 측정되는 데이터들에 대한 저장 및 검색을 효율적으로 하기 위한 플래시 메모리 공간 관리 기법을 제안한다. 플래시 메모리는 외부 충격에 강하고, 비휘발성이며 접근이 빠른 장점이 있지만, 덮어쓰기 및 쓰기 횟수가 제한되는 단점이 있다. 이러한 특성으로 플래시 메모리는 기존의 저장매체와는 다른 관리 방법이 요구되었고 지금까지의 센서노드에서는 플래시 메모리를 사용 하지 않았다. 본 논문에서는 센서노드안의 플래시 메모리에서 순차적으로 측정되는 데이터를 관리하기 위해 LFS(Log-Structured File System)방식을 제안한다. 그리고 순차적으로 정렬된 데이터에 효율적인 검색방법을 제시하고, 이를 ZigbeX Mote의 TinyOS안에서 NesC로 구현하였다.

• Journal of Internet of Things and Convergence
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• v.10 no.3
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• pp.19-24
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• 2024

Recent advances in large-scale data processing technologies such as big data, cloud computing, and artificial intelligence have increased the demand for high-performance storage devices in data centers and enterprise environments. In particular, the fast data response speed of storage devices is a key factor that determines the overall system performance. Solid state drives (SSDs) based on the Non-Volatile Memory Express (NVMe) interface are gaining traction, but new bottlenecks are emerging in the process of handling large data input and output requests from multiple hosts simultaneously. SSDs typically process host requests by sequentially stacking them in an internal queue. When long transfer length requests are processed first, shorter requests wait longer, increasing the average response time. To solve this problem, data transfer timeout and data partitioning methods have been proposed, but they do not provide a fundamental solution. In this paper, we propose a dual queue based scheduling scheme (DQBS), which manages the data transfer order based on the request order in one queue and the transfer length in the other queue. Then, the request time and transmission length are comprehensively considered to determine the efficient data transmission order. This enables the balanced processing of long and short requests, thus reducing the overall average response time. The simulation results show that the proposed method outperforms the existing sequential processing method. This study presents a scheduling technique that maximizes data transfer efficiency in a high-performance SSD environment, which is expected to contribute to the development of next-generation high-performance storage systems

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.122-122
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• 2008

Recently, Metal/Alumina/Silicon-Nitride/Silicon-Oxide/Silicon (MANOS) structures are one of the most attractive candidates to realize vertical scaling of high-density NAND flash memory [1]. However, as ANO layers are miniaturized, negative and positive bias temperature instability (NBTI/PBTI), such as the flat band voltage shift, ${\Delta}V_{FB}$, the interfacial trap density increase, ${\Delta}D_{it}$, the gate leakage current, ${\Delta}I_G$. and the retention characteristics, in MONOS capacitors, becomes an important issue in terms of reliability. It is well known that tunnel oxide degradation is a result of the oxide and interfacial traps generation during FN (Fowler-Nordheim) stress [2]. Because the bias temperature stress causes an increase of both interfacial-traps and fixed oxide charge could be a factor, witch can degrade device reliability during the program and erase operation. However, few studies on NBTI/PBTI have been conducted on improving the reliability of MONOS devices. In this work, we investigate the effect of post-annealing gas on bias temperature instability (BTI), such as the flat band voltage shift, ${\Delta}V_{FB}$, the interfacial trap density shift, ${\Delta}I_G$ retention characteristics, and the gate leakage current characteristics of MANOS capacitors. MANOS samples annealed at $950^{\circ}C$ for 30 s by a rapid thermal process were treated via additional annealing in a furnace, using annealing gases $N_2$ and $N_2-H_2$ (2 % hydrogen and 98 % nitrogen mixture gases) at $450^{\circ}C$ for 30 min. MANOS samples annealed in $N_2-H_2$ ambient had the lowest flat band voltage shift, ${\Delta}V_{FB}$ = 1.09/0.63 V at the program/erase state, and the good retention characteristics, 123/84 mV/decade at the program/erase state more than the sample annealed at $N_2$ ambient.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.54-62
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• 2015

Although NAND flash-based SSD (Solid-State Drive) provides superior performance in comparison to HDD (Hard Disk Drive), it has a major drawback in write endurance. As a result, the lifetime of SSD is determined by the workload and thus it becomes a big challenge in current technology trend of such as the shifting from SLC (Single Level Cell) to MLC (Multi Level cell) and even TLC (Triple Level Cell). Most previous studies have dealt with wear-leveling or improving SSD lifetime regarding hardware architecture. In this paper, we propose the optimal configuration of host I/O stack focusing on file system, I/O scheduler, and link power management using JEDEC enterprise workloads in terms of WAF (Write Amplification Factor) which represents the efficiency perspective of SSD life time especially for host write processing into flash memory. Experimental analysis shows that the optimum configuration of I/O stack for the perspective of SSD lifetime is MinPower-Dead-XFS which prolongs the lifetime of SSD approximately 2.6 times in comparison with MaxPower-Cfq-Ext4, the best performance combination. Though the performance was reduced by 13%, this contributions demonstrates a considerable aspect of SSD lifetime in relation to I/O stack optimization.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.56-63
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• 2010

This work proposes a 12b 100MS/s 0.13um CMOS pipeline ADC for battery-powered mobile video applications such as DVB-Handheld (DVB-H), DVB-Terrestrial (DVB-T), Satellite DMB (SDMB), and Terrestrial DMB (TDMB) requiring high resolution, low power, and small size at high speed. The proposed ADC employs a three-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. A single shared and switched op-amp for two MDACs removes a memory effect and a switching time delay, resulting in a fast signal settling. A two-step reference selection scheme for the last-stage 6b FLASH ADC reduces power consumption and chip area by 50%. The prototype ADC in a 0.13um 1P7M CMOS technology demonstrates a measured DNL and INL within 0.40LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 60.0dB and a maximum SFDR of 72.4dB at 100MS/s, respectively. The ADC with an active die area of 0.92 $mm^2$ consumes 24mW at 1.0V and 100MS/s. The FOM, power/($f_s{\times}2^{ENOB}$), of 0.29pJ/conv. is the lowest of ever reported 12b 100MS/s ADCs.