• The Journal of the Acoustical Society of Korea
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• v.19 no.4
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• pp.45-51
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• 2000

This paper describes real-time implementation of a multi-channel G.729A speech coder using a 16 bit fixed-point Digital Signal Processor (DSP) and its application to a Voice Mailing Service (VMS) system. TMS320C549 by Texas Instruments was used as a fixed point DSP chip and a 4 channel G.729A coder was implemented on the chip. The implemented coder required 14.5 MIPS for the encoder and 3.6 MIPS for the decoder at each channel. In addition, memories required by the coder were 9.88K words and 1.69K words for code and data sections, respectively. As a result, the developed VMS system that accommodates two DSP chips was able to support totally 8 channels. Experimental results showed that the our multi-channel coder passes all of test vectors provided by ITU-T.

• Proceedings of the KIEE Conference
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• 2005.10c
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• pp.98-100
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• 2005

DSPs used at motor control are usually fixed point processor. They need scaling because they cannot excute floating point calculation. Scaling for floating point calculation makes the DSP's speed down, complex coding and etc. Therefore the IQ math is adopted. IQ math makes the fixed point processor possible to calculate the floating point math. In addition, IQ math can reduce memory usage and be more faster than that without IQ math. It seems that IQ math is appropriate in motor position control. In comparison of the position calculation between the IQ math, math function and the sine table, the method using IQ math is superior than other methods.

• 한국신재생에너지학회:학술대회논문집
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• 2005.11a
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• pp.665-665
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• 2005

The existing DSP for utility interactive photovoltaic generation system control generally uses floating point process type. Because it is easy to use for number crunching, however, it is too late and too expensive. Fixed point process DSP TMS320F2812, has high control speed and is rather inexpensive. A very complicated real system can be simulated using hardware-in-the-loop (HIL) system in a virtual environment Therefore, HIL system can speed up research and development process with a little effort. Also current DSP for utility interactive photovoltaic generation system adopts floating point process type, which is easy to use for number crunching. However, fixed point process DSF, TMS320F2812, has high control speed and is rather inexpensive. This paper presents more efficient method for MPPT control using TMS320F2812 along with HIL System.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.873-874
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• 2006

In this paper, we have developed a ventricular fibrillation detection system based on DSP processor. The developed system was able to detect VF in real time correctly and quickly. We compared the performance of the floating point simulation with that of fixed point simulation. The computational cost of fixed point simulation was remarkably reduced than that of floating point simulation.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.250-253
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• 2000

In this paper, we Implement a new arithmetic computation for MPEG audio data to overcome the limitations of real number processing in the fixed-point arithmetics, such as: overheads in processing time and power consumption. We aims at efficiently dealing with real numbers by extending the fixed-point arithmetic manipulation for floating-point numbers in MPEG audio data, and implementing the DSP libraries to support the manipulation and computation of real numbers with the fixed-point resources.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.12
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• pp.31-39
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• 1998

This paper presents the design and implementation of a new multimedia fixed-point DSP (MDSP) core for portable multimedia applications. The MDSP instruction set is designed through the analysis of multimedia algorithms and DSP instruction sets. The MDSP architecture employs parallel processing techniques, such as SIMD and vector processing as well as DSP techniques. The instruction set can handle various data formats and MDSP can perform two MAC operations in parallel. The switching network and packing network can increase the performance by overlapping data rearrangement cycles with computation cycles. We have designed Verilog HDL models and the 0.6 $\mu\textrm{m}$ Samsung KG75000 SOG library is used. The total gate count is 68,831 and the clock frequency is 30 MHz.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1211-1214
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• 1998

Real-time implementation of Conjugate-Structure Algebraic CELP(CS-ACELP) is presented. ITU-T Study Group(SG) 15 has standardized the CS-ACELP speech coding algorithm as G.729. A real-time implementation of the CS-ACELP is achieved using 16 bit fixed point DSP16210 Digital Signal Processor (DSP) of Lucent Technologies. The speech coder has been implemented in the bit-exact manner using the fixed point CS-ACELP C source which is the part of the G.729 standard. To provide a multi-channel vocoder solution to digital communication system, we try to minimize the complexity(e.g., MIPS, ROM, RAM) of CS-ACELP. Our speech coder shows 15.5 MIPS in performance which enables 4 channel CS-ACELP to be processed with one DSP16210.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.6
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• pp.1195-1201
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• 2005

This paper deals with procedures and results for teal time implementation of G.729 speech coder and channel coder including convolution codec, viterbi decoder, and interleaver using a fixed point DSP chip for radio communication systems. We described the method for real-time implementation based on integer simulation results and explained the implemented results by quality performance and required complexity for real-time operation. The required complexity was 24MIPS and 9MIPS in computational load, and 12K words and 4K words in execution code length for speech and channel. The functional evaluation was performed into two steps. The one was bit exact comparison with a fixed point C code, the other was executed by actual speech samples and error test vectors. Unlik other results such as individual implementation, We implemented speech and channel coders on a DSP chip with 160MIPS computation capability and 64 K words memory on chip. This results outweigh the conventional methods in the point of system complexity and implementation cost for radio communication system.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.1
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• pp.95-103
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• 2009

We improve the performance of WCDMA repeater by cancelling the feedback interference radio signal under the fixed point implementation. Floating-point DSP or FPGA to implement the ICS algorithm may have an disadvantage of high cost, To solve this problem, we suggest the ICS algorithm based on LMS under fixed point operation, and show the validity of our results by comparing with the floating-point results through numerical simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.3
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• pp.335-341
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• 1998

In this paper, we present a real time implementation of CS-ACELP(Conjugate Structure Algebraic Code Excited Linear Prediction) speech coder. ITU-T has standardized the CS-ACELP algorithm as G.729. Areal-time implementation of CS-ACELP speech coder algorithm is achieved using 16 bit fixed-point DSP chip. To implement in fixed-point DSP Chip, integer simulation of CS-ACELP algorithm is used. Furthermore. input/output function and communication function included in CS-ACELP speech coder is described. We develope CS-ACELP speech coder in DSP evaluation board and evaluate in IMT-2000 Test-bed.