• Korean Journal of Materials Research
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• v.11 no.4
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• pp.290-293
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• 2001

The SrBi$_2$Nb$_2$O$_{9}$ (SBN) thin films were deposited on p-type(100) Si substrates by rf magnetron sputtering to confirm the Possibility of Pt/SBN/Si structure for the application of nondestructive read out ferroelectric random access memory (NDRO- FRAM). The SBN thin films were deposited by co-sputtering method with Sr$_2$Nb$_2$O$_{7}$ (SNO) and Bi$_2$O$_3$ ceramic targets. The SBN thin films deposited at room temperature were annealed at $700^{\circ}C$ for 1hr in $O_2$ ambient. The structural and electrical properties of SBN with different power ratios of targets were measured by x-ray diffraction(XRD), scanning electron microscopy(SEM), capacitance-voltage(C-V), and current-voltage(I-V). The C-V curves of the SBN films showed hysteresis curves of a clockwise rotation showing ferroelectricity. When the Power ratio of the SNO/Bi$_2$O$_3$ targets was 120 W/100 W, the SBN thin films had excellent electrical properties. The memory window of SBN thin film was 1.8 V-6.3 V at applied voltage of 3 V-9 V and the leakage current density was 1.5 $\times$ 10$^{-7}$ A/$\textrm{cm}^2$ at applied voltage of 5 V The composition of SBN thin films was analysed by electron probe X-ray micro analyzer(EPMA) and the atomic ratio of Sr:Bi:Nb with pawer ratio of 120 W/100 W was 1:3:2.

• Korean Journal of Materials Research
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• v.12 no.12
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• pp.962-966
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• 2002

The $SrBi_2$$Nb_2$$O_{9}$ (SBN) thin films were deposited with $SrNb_2$$O_{6}$ / (SNO) and $Bi_2$$O_3$ targets by co-sputtering method. For the growth of SBN thin films, we adopted the various power ratios of two targets; the power ratios of the SNO target to $Bi_2$$O_3$ target were 100 W : 20 W, 100 W : 25 W, and 100 W : 30 W during sputtering the SBN films. We found that the electrical properties of SBN films were greatly dependent on Bi content in films. The $Bi_2$Pt and $Bi_2$$O_3$ phase as second phases occurred at the films with excess Bi content greater than 2.4, resulting in poor ferroelectric properties. The best growth condition of the SBN films was obtained at the power ratio of 100 W : 25 W for the two targets. At this condition, the crystallinity and electrical properties of the films were improved at even low annealing temperature as $700^{\circ}C$ for 1h in oxygen ambient and the Sr, Bi and Nb component in the SBN films were about 0.9, 2.4, and 1.8 respectively. From the P-E and I-V curves for the specimen, the remnant polarization value ($2P_{r}$) of the SBN films was obtained about 6 $\mu$C/c $m^2$ at 250 kV/cm and the leakage current density of this thin film was $2.45$\times$10^{-7}$ $A/cm^2$ at an applied voltage of 3 V.V.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.319-322
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• 2003

To match the charge induced by the insulators $CeO_2$ with the remanent polarization of ferro electric SBT thin films, areas of Pt/SBT/Pt (MFM) and those of $Pt/CeO_2/Si$ (MIS) capacitors were ind ependently designed. The area $S_M$ of MIS capacitors to the area $S_F$ of MFM capacitors were varied from 1 to 10, 15, and 20. Top electrode Pt and SBT layers were etched with for various area ratios of $S_M\;/\;S_F$. Bottom electrode Pt and $CeO_2$ layers were respectively deposited by do and rf sputtering in-situ process. SBT thin film were prepared by the metal orgnic decomposition (MOD) technique. $Pt(100nm)/SBT(350nm)/Pt(300nm)/CeO_2(40nm)/p-Si$ (MFMIS) gate structures have been fabricated with the various $S_M\;/\;S_F$ ratios using inductively coupled plasma reactive ion etching (ICP-RIE). The leakage current density of MFMIS gate structures were improved to $6.32{\times}10^{-7}\;A/cm^2$ at the applied gate voltage of 10 V. It is shown that in the memory window increase with the area ratio $S_M\;/\;S_F$ of the MFMIS structures and a larger memory window of 3 V can be obtained for a voltage sweep of ${\pm}9\;V$ for MFMIS structures with an area ratio $S_M\;/\;S_F\;=\;6$ than that of 0.9 V of MFS at the same applied voltage. The maximum memory windows of MFMIS structures were 2.28 V, 3.35 V, and 3.7 V with the are a ratios 1, 2, and 6 at the applied gate voltage of 11 V, respectively. It is concluded that ferroelectric gate capacitors of MFMIS are good candidates for nondestructive readout-nonvolatile memories.

• KOREAN JOURNAL OF PACKAGING SCIENCE & TECHNOLOGY
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• v.12 no.2
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• pp.117-123
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• 2006

To mass-product useful biopolymer films, chitosan/gelatin blend films were prepared by solution casting method. Effect of mixing ratio, tensile strength(TS), elongation(${\Delta}E$) at break, total color difference(E), water vapor permeability(WVP) and oxygen permeability(OP) on chitosan/gelatin blend films properties were investigated. TS, ${\Delta}E$, E, WVP and OP values of chitosan/gelatin blend films were 43.43-38.30 MPa, 9.02-15.09%, 1.28-3.81, $0.8420-0.9673ng{\cdot}m/m^2{\cdot}s{\cdot}Pa$ and $1.5472{\times}10^{-7}-1.5424{\times}10^{-7}mL{\cdot}{\mu}m/m^2{\cdot}s{\cdot}Pa$, respectively. TS of the blend films decreased, while E and E of the blend films increased with increasing chitosan content. WVP and OP of the blend films did not show any significant relationship with mixing ratio and thickness of the blend films. OP of the blend films were lower than those of low density polyethylene and oriented polypropylene.

• Journal of the Korean Vacuum Society
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• v.11 no.3
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• pp.176-182
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• 2002

Amorphous $TiO_2$ thin films were deposited on glass substrates by ion beam sputtering in which the ratio of $O_2$/Ar gas used as discharged gas was varied from 0 to 2. After optical and microstructure properties and chemical composition of thin films was analyzed, antireflection coating layers were fabricated with $SiO_2$/$TiO_2$ multi-layers. Thin films deposition was performed at room temperature and ion beam voltage and ion current density for sputtering of target were fixed at 1.2 kV and 200 $\mu\textrm{A}/\textrm{cm}^2$, respectively. Refractive indexs of the deposited $TiO_2$films were 2.40-2.45 at a wavelength of 633 nm. $TiO_2$films had high transmission and stoichiometry when ratio of $O_2$/Ar was 1. Rms roughness of deposited $TiO_2$ film was below 7 $\AA$. In excessive $O_2$ environments, however Rms roughness increased over 50 $\AA$. Transmittance decreased by scattering of rough surface. Reflectance of $SiO_2$/$TiO_2$multi-layers was below 1% in visible light.

• Journal of the Korean Vacuum Society
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• v.9 no.4
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• pp.411-418
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• 2000

$Al_2O_3$ thin films of 300 nm thickness were deposited at room temperature using DC reactive sputtering with variation of the $O_2$ content in the sputtering gas from 30% to 70%. Regardless of the $O_2$ content in the sputtering gas, the sputtered $Al_2O_3$ films were amorphous and exhibited the refractive index of 1.58. When the $O_2$ content in the sputtering gas was higher than 50%, the $Al_2O_3$ films exhibited excellent transmittance of about 98% at 550 nm wavelength. However, the transmittance decreased to about 94% for the $Al_2O_3$ films deposited with the sputtering gas of the 30% and 40% $O_2$contents. The optimum dielectric properties (dielectric constant of 10.9 and loss tangent of 0.01) was obtained for the $Al_2O_3$ film deposited with the sputtering gas of the 50% $O_2$ content. When the $O_2$ content in the sputtering gas was within 40% to 60%, the $Al_2O_3$ films exhibited no shift of flatband voltage $V_{FB}$ in C-V curves and exhibited leakage current density lower than $10^{-5}\textrm{A/cm}^2$ at 150 kV/cm.

• Applied Chemistry for Engineering
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• v.4 no.2
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• pp.393-402
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• 1993

Redox flow secondary battery have been studied actively as one of the most promising electrochemical energy storage devices for a wide range of applications, such as electric vehicles, photovoltaic arrays, and excess power generated by electric power plants. In all-vanadium redox flow battery using solution of vanadium-sulfuric acid as a active material, the difficulty in developing an efficient ion selective membrane can still be identified. The asymmetric cation exchange membrane(M-30) as a separator of all-vanadium redox flow battery which were obtained by the reaction of chlorosulfonation for 30 minutes under the irradiation of UV, showed its superiority in the transport number of 0.94 and electrical resistivity of $0.5{\Omega}{\cdot}cm^2$. The base membrane were prepared by lamination a low density polyethlene film of $10{\mu}m$ thickness on polyolefin membrane(HIPORE 120). The electrical resistivity of M-30 membrane in real solution of vanadium-sulfuric acid was $3.79{\Omega}{\cdot}cm^2$ and it was similar to that of Nafion 117 membrane. Also the cell resistivity was $6.6{\Omega}{\cdot}cm^2$and lower than that of Nafion 117. In considertion of electrochemical properties and costs of membranes, M-30 membrane was better than that of Nafion 117 and CMV of Asahi glass Co. as a separator of all-vanadium redox flow battery.

• Food Science of Animal Resources
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• v.33 no.3
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• pp.390-394
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• 2013

The aim of this study was to determine the optimal storage condition of pre-packed Hanwoo beef without freezing. Hanwoo loin was purchased from a local distributor at 48 h after slaughter, then sliced in $1.5{\pm}0.5$ cm thickness, and packed in a polyethylene (PE) tray covered with linear low-density polyethylene (LLDPE) film. The studied factors to set the optimal storage condition were chamber temperature (5, 2.5 and $-1^{\circ}C$ for 14 d), cooling method (direct and indirect cooling system), and ultraviolet (UV) light irradiation for beef surface sterilization (0, 30, 60, and 120 min). The changes of pH, thiobarbituric acid reactive substances (TBARS) and number of aerobic bacteria were measured during storage. Beef samples stored in $-1^{\circ}C$ showed the minimal increasing rate in TBARS and microbial growth. After 15 d of storage, there was no significant difference in pH and TBARS values. However, the microbial population of beef stored in direct type cooling chamber ($4.25{\pm}0.66$ Log CFU/g) was significantly lower than that of beef stored in indirect type chamber ($6.47{\pm}0.08$ Log CFU/g) (p<0.05). After 4 d of storage, 60 or 120 min UV light irradiated beef samples showed significantly lower microbial population, and at 14 d of storage, 60 min UV irradiated beef sample showed significantly lower microbial population ($3.14{\pm}0.43$ Log CFU/g) than control ($4.46{\pm}0.13$ Log CFU/g) (p<0.05). However, TBARS values of 60 or 120 min UV light irradiated beef samples were significantly higher than non-irradiated beef sample after 4 d of storage (p<0.05).

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.