• Proceedings of the KIEE Conference
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• 2000.07a
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• pp.215-217
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• 2000

Protective relay play a crucial role in the proper operation of a power system, and the reliable transfer of electrical power. This paper deals with the design and implementation of a digital protective relay on a single chip. Implementation on the FPGA(Field Programmable Gate Array) of the chip of digital protective relay. This protective relaying chip monitors the frequency and the voltage and current of the power system. And report the voltage, the current. the frequency, active power and reactive power.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.8C
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• pp.812-818
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• 2002

반도체 기술과 멀티기디어 통신기술이 발달하면서 고품위의 영상과 다중 채널의 오디오에 관심을 갖게되었다. 특히 DVD 시장의 급성장으로 인하여 고품질의 영상 및 오디오 필요성이 중요한 기술로 대두되었다. MPEG-Audio 표준안은 어떠한 비트율도 지원한다. 본 논문에서는 MPEG-Audio의 핵심부분인 필터부분을 DALUT (Distributed Arithmetic Look-Up Table)방식을 사용하여 FPGA(Field Programmable Gate Array)에 구현하였다. 고속 필터를 설계하기 위해서 승산기 대신에 DALUT를 사용하였으며 최소 10㎒에서 최대 30㎒ 사이에서 동작한다. 본 논문의 설계는 모두 VHDL로 구현하였으며, 알고리즘 검증은 C언어를 사용하였다. VHDL의 시뮬레이션은 ALDEC사의 Active-HDL5.1과 Synopsys사의 vhdlsim을 사용하였고, 합성은 Synopsys사의 design-analyzer를 사용하였다. 타겟 라이브러리는 XILINX사의 XC4010E, XC4020EX, XC4052XL을 사용하였으며, P＆R 툴은 XACT Ml.4를 사용하였다.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1358-1361
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• 2002

In this paper, we propose a new architecture of digital automatic gain control (AGC) for a wideband code division multiple access (WCDMA) receiver. The feature of the proposed architecture is simplicity, in that it does not utilize complicated mathematical functions such as log and its inverse. When the proposed algorithm is implemented using a field programmable gate array (FPGA) device, the number of slices used to implement is 130 over the total of 5120 slices (less than 3%) with 61.44 ㎒ clock. This algorithm has been successfully applied to commercial WCDMA base stations.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1161-1164
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• 2003

We have developed an optimization algorithm based formulation for performing efficient time driven simultaneous place and route for FPGAs. Field programmable gate array(FPGAs) provide of drastically reducing the turn-around time for digital ICs, with a relatively small degradation in performance. For a variety of application specific integrated circuit application, where time-to-market is most critical and the performance requirement do not mandate a custom or semicustom approach, FPGAs are an increasingly popular alternative. This has prompted a substantial amount of specialized synthesis and layout research focused on maximizing density, minimizing delay, and minimizing design time.

• Journal of IKEEE
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• v.18 no.4
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• pp.566-571
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• 2014

A safety class field programmable gate array based system in nuclear power plant has been developed to improve the diversity. Testbench is necessary to satisfy the technical reference, IEC-62566, for verification and validation of register transfer level code. We use the open verification methodology(OVM) developed by standard body. We show that our testbench can use random input for test. And also we show that reusability of block level testbench for the integration level testbench, which is very efficient for large scale system like nuclear reactor protection system.

• Proceedings of the KIPE Conference
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• 2006.06a
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• pp.467-469
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• 2006

최신의 디지털 방식 UPS(Uninterruptible Power Supply)는 10여 년 전의 아날로그 UPS에 비해 많은 설계 요인들로 인해 복잡해지고 있다. 고속-고성능의 DSP(Digital Signal Process), 다수의 I/O를 위한 FPGA(Field-Programmable Gate Array), 다기능의 사용자 인터페이스 그리고 다양한 통신 등이 그 예라고 할 수 있다. 임베디드 디자인이 이렇게 복잡해지면서 하드웨어나 소프트웨어를 신뢰성 있게 테스트하기에 기존 방법으로는 충분치 않게 되었다. 본문에서는 NI(National Instruments)의 버추얼 인스트루먼트(Virtual Instrument) 기술을 이용하여 자동화된 테스트 시스템에 대해 기술한다.

• Proceedings of the Korean Information Science Society Conference
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• 2006.10d
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• pp.502-505
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• 2006

본 논문은 고해상도의 영상을 처리하는 이동기기 등에 사용되는 SoC(System On a Chip)에 구현이 용이한 효과적인 화질 향상 (잡음감소와 윤곽강조) 을 위한 방법과 구조에 대한 것이다. 최근 이동기기의 발전과 진화에 따라 여러 형태의 이동기기가 개발되고 있는데 그 중 최근 인기를 끌고 있는 포터블 미디어 플레이어 (PMP)나 HD(Hight Definition)급 camcorder 등이 고해상도의 영상을 처리하는 이동기기로 분류될 수 있다. 이러한 이동기기에서 고해상도 영상에 대한 화질 향상을 기존의 복잡한 방법을 사용해 처리한다면 메모리 대역폭이나 하드웨어 크기 등의 증가로 이동기기에서 구현하는데 어려움이 따른다. 이에 본 논문에서는 이러한 이동기기에서의 고해상도의 화질 향상을 입력영상의 종류에 따라 선택적으로 메모리 대역폭 사용 없이 하드웨어 크기를 최소화하여 FPGA (field programmable gate array)나 ASIC (application specific integrated circuit)으로 구현이 용이하도록 하는 방법과 구조에 대해 설명하고 실제 영상을 가지고 실험한 결과로 주관적 화질 향상 효과를 가져 온 것을 확인할 수 있었다.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.533-536
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• 2000

In this paper, we proposed high performance packet forwarding engine for asynchronous transfer mode(ATM) based gigabit routers. The forwarding engine is based on ATM switch and accommodates four 622Mbps ports. The forwarding engine has been designed to be able to process the Intemet protocol(IP) packet at 2.5Gbps using the pipelined If header processing and lookup control mechanism. For high performance packet forwarding, we used content addressable memory(CAM) based routing coprocessor operating in hardware and implemented the pipelined lookup control function into a field programmable gate array(FPGA). The pipelined packet header processing mechanism enhanced the forwarding performance of the If packets ingressed from four different 622Mbps ports. Moreover, the If lookup controller designed to have the performance up to 12.5Mpps. The proposed forwarding engine is also designed to support differentiated services(DS) and multiprotocol label switching(MPLS).

• Journal of Power Electronics
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• v.11 no.5
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• pp.751-758
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• 2011

This paper presents an effective robust predictive control scheme for the active power filter (APF) using a smith-predictor based current regulator, which show superior features when compared to proportional-integral (PI) controllers in terms of an enhanced closed-loop bandwidth and an improved current tracking accuracy. A moving average filter (MAF) is implemented using a field programmable gate array (FPGA) for signal pre-processing to eliminate the switching ripple contamination. An adaptive linear neural network (ADALINE) is used for individual harmonic estimation to achieve selective compensation purpose. The effectiveness and validity of the devised control algorithm are confirmed by extensive simulation and experimental results.

• Journal of Power Electronics
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• v.15 no.4
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• pp.964-973
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• 2015

This paper presents a simple approach for the selective harmonic elimination (SHE) of multilevel inverter based on the transistor-clamped H-bridge (TCHB) family. The SHE modulation is derived from the sinusoidal voltage-angle equal criteria corresponding to the optimized switching angles. The switching angles are computed offline by solving transcendental non-linear equations characterizing the harmonic contents using the Newton-Raphson method to produce an optimum stepped output. Simulation and experimental tests are conducted for verification of the analytical solutions. An Altera DE2 field-programmable gate array (FPGA) board is used as the digital controller device in order to verify the proposed SHE modulation in real-time applications. An analysis of the voltage total harmonic distortion (THD) has been obtained for multiple output voltage cases. In terms of the THD, the results showed that the higher the number of output levels, the lower the THD due to an increase number of harmonic orders being eliminated.