• KSII Transactions on Internet and Information Systems (TIIS)
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• v.18 no.8
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• pp.2366-2380
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• 2024

In this study, a high-speed template matching system is proposed for wafer-vision alignment. The proposed system is designed to rapidly locate markers in semiconductor equipment used for wafer-vision alignment. We optimized and implemented a template-matching algorithm for the high-speed processing of high-resolution wafer images. Owing to the simplicity of wafer markers, we removed unnecessary components in the algorithm and designed the system using a field-programmable gate array (FPGA) to implement high-speed processing. The hardware blocks were designed using the Xilinx ZCU104 board, and the pyramid and matching blocks were designed using programmable logic for accelerated operations. To validate the proposed system, we established a verification environment using stage equipment commonly used in industrial settings and reference-software-based validation frameworks. The output results from the FPGA were transmitted to the wafer-alignment controller for system verification. The proposed system reduced the data-processing time by approximately 30% and achieved a level of accuracy in detecting wafer markers that was comparable to that achieved by reference software, with minimal deviation. This system can be used to increase precision and productivity during semiconductor manufacturing processes.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.12
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• pp.1554-1563
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• 1999

This paper presents the design of high speed processor for a sequence logic control using field programmable gate array(FPGA). The sequence logic controller is widely used for automating a variety of industrial plants. The FPGA designed by VHDL consists of program and data memory interface block, input and output block, instruction fetch and decoder block, register and ALU block, program counter block, debug control block respectively. Dedicated clock inputs in the FPGA were used for high speed execution, and also the program memory was separated from the data memory for high speed execution of the sequence instructions at 40 MHz clock. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 16 bits or 32 bits respectively. And the real time debug operation was implemented for easy debugging the designed processor. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to sequence control system with inputs and outputs of 256 points. The designed processor for the sequence logic was compared with the control system using the DSP(TM320C32-40MHz) and conventional PLC system. The designed processor for the sequence logic showed good performance.

• Journal of Korea Society of Digital Industry and Information Management
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• v.9 no.2
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• pp.55-61
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• 2013

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing. The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC) (circuit diagrams were previously used to specify the configuration, as they were for ASICs, but this is increasingly rare). Contemporary FPGAs have large resources of logic gates and RAM blocks to implement complex digital computations. In this paper, we implement a system of digital instrumentation using FPGA. This system consists of the trigger part, memory address controller part, control FSM part, Encoder part, LCD controller part. The hardware implement using FPGA and the verification of the operation is done in a PC simulation. The proposed hardware was mapped into Cyclone III EP2C5Q208 from Altera and used 1,700(40%) of Logic Element (LE). The implemented circuit used 24,576-bit memory element with 6-bit input signal. The result from implementing in hardware (FPGA) could operate stably in 140MHz.

• Journal of the Korea Institute of Military Science and Technology
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• v.25 no.2
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• pp.151-159
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• 2022

In this paper, we implement a digital multi-beamformer using FPGA(Field Programmable Gate Array) which has advantages in parallel and real-time data processing. This is accomplished through the use of not only high-speed data communication but also multiple beam forming, which is currently required by MFR(Multi Function Radar). As a result, the beamformer can process 24 Gbps throughput in real-time and form 5 digital beams at the same time. It is also compared to the results of Matlab simulations. We demonstrate how an implemented beamformer can be used in an MFR system by using a digital array antenna.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.2
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• pp.125-134
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• 1994

This paper proposes a new top-down technology mapping algorithm for minimizing the chip area and the path delay time of lookup table-based field programmable gate array(FPGA). First, we present the decomposition and factoring algorithm using common subexpre ssion which minimizes the number of basic logic blocks and levels instead of the number of literals. Secondly, we propose a cube packing algorithm considering the decomposition of gates which exceed m-input lookup table. Previous approaches perform the cube packing and the gate decomposition independently, and it causes to increase the number of basic logic blocks. Lastly, the efficiency.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.11
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• pp.5427-5433
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• 2012

In this paper a ultrasonic level meter for accurately and simply measuring oil levels of vehicle transmission is developed and its effectiveness is shown by experiments. By using a FPGA, all digital signal processes for the oil level calculation is fulfilled, and the programming on a FPGA project IDE enables very short developing time. And besides, analog circuits including a transmit/receive switch, multi-stage active filters and an envelope detect circuit are designed to process low-level ultrasonic echo signal. Under experiments, the designed level meter has proven to have the accuracy of about within 1[mm] scale.

• Journal of information and communication convergence engineering
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• v.13 no.3
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• pp.145-151
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• 2015

We describe in this paper a hardware-based improvement scheme of a real-time automatic speech recognition (ASR) system with respect to speed by designing a parallel feature extraction algorithm on a Field-Programmable Gate Array (FPGA). A computationally intensive block in the algorithm is identified implemented in hardware logic on the FPGA. One such block is mel-frequency cepstrum coefficient (MFCC) algorithm used for feature extraction process. We demonstrate that the FPGA platform may perform efficient feature extraction computation in the speech recognition system as compared to the generalpurpose CPU including the ARM processor. The Xilinx Zynq-7000 System on Chip (SoC) platform is used for the MFCC implementation. From this implementation described in this paper, we confirmed that the FPGA platform is approximately 500× faster than a sequential CPU implementation and 60× faster than a sequential ARM implementation. We thus verified that a parallelized and optimized MFCC architecture on the FPGA platform may significantly improve the execution time of an ASR system, compared to the CPU and ARM platforms.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.167-174
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• 2012

In this paper a ultrasonic oil level meter for measuring oil levels of vehicle transmissions is designed and its effectiveness is shown by experiments. On a FPGA(Field Programmable Gate Array) project IDE(Integrated Development Environment), all digital circuits for the meter is designed using a FPGA, which enables simplicity and high performance of the meter as well as short developing time. Also, power supplying circuit and analog circuits to process low voltage ultrasonic echo signal are designed and simulated. Under experiments, the designed level meter is verified to provide accuracy to within 1mm.

• Journal of Power Electronics
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• v.10 no.4
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• pp.342-350
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• 2010

Randomizing the switching frequency (RSF) to reduce the electromagnetic interference (EMI) of switching power converters is a well-known technique that has been previously discussed. The randomized pulse position (RPP) technique, in which the switching frequency is kept fixed while the pulse position (the delay from the starting of the switching cycle to the turn-on instant within the cycle) is randomized, has been previously addressed in the literature for the same purpose. This paper presents a double-hybrid technique (DHB) for EMI reduction in dc-dc switching regulators. The proposed technique employed both the RSF and the RPP techniques. To effectively spread the conducted-noise frequency spectrum and at the same time attain a satisfactory output voltage quality, two parameters (switching frequency and pulse position) were randomized, and a third parameter (the duty ratio) was controlled by a digital compensator. Implementation was achieved using field programmable gate array (FPGA) technology, which is increasingly being adopted in industrial electronic applications. To evaluate the contribution of the proposed DHB technique, investigations were carried out for each basic PWM, RPP, RSF, and DHB technique. Then a comparison was made of the performances achieved. The experimentally investigated features include the effect of each technique on the common-mode, differential-mode, and total conducted-noise characteristics, and their influence on the converter’s output ripple voltage.

• Journal of Korea Society of Digital Industry and Information Management
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• v.9 no.1
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• pp.95-102
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• 2013

This paper covers nulling algorithm. In this algorithm, we assume that nulling points are already known. In general, nulling algorithm using matrix equation was utilized. But, this algorithm is pointed out that computational complexity is disadvantage. So, we choose gradient method to reduce the computational complexity. In order to further reduce the computational complexity, we propose approximate gradient method using characteristic of trigonometric functions. The proposed method has same performance compared with conventional method while having half the amount of computation when the number of antenna and nulling point are 20 and 1, respectively. In addition, we could virtually eliminate the trigonometric functions arithmetic. Trigonometric functions arithmetic cause a big problem in actual implementation like FPGA processor(Field Programmable gate array). By utilizing the above algorithm in a multi-cell environment, beamforming gain can be obtained and interference can be reduced at same time. By the above results, the algorithm can show excellent performance in the cell boundary.