• Journal of KIISE:Computing Practices and Letters
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• v.16 no.6
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• pp.637-647
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• 2010

Recent embedded systems are being more complicated due to their hierarchical software architecture including operating systems. The performance of such complicated software architecture could not be well analyzed through separate analysis of each software layer; the combined effect and the interactions among the whole software layers should be considered. In this paper, we show the design and implementation of a performance analysis framework that enables hierarchical analysis of performance of Linux-based embedded systems considering interactions among the software layers. By using the proposed framework, we can obtain useful run-time information about a hierarchical software structure which usually consists of user-defined function layer, library function layer, system call layer, and kernel events layer. Experimental results reveal that the proposed framework could accurately identify the performance bottlenecks with the corresponding software layers during executions of target applications through the accompanying sub-steps of the analysis: the actual execution paths, the execution time of each observed event in each software layer, and the control flows across the software layers.

• The KIPS Transactions:PartD
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• v.13D no.3 s.106
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• pp.399-404
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• 2006

A real-time system is used for various systems from small embedded systems to distributed enterprise systems. Because it has a characteristic that provides a service on time, developers should make efforts to keep this property about time when developing real-time applications. As the result of research about real-time system indicates, TMO model supports various functions for time processing according to the real-time concept. And it guarantees response time which developers defined. So developers need a point of reference to define deadline and check the correctness of time. This paper proposes an improved PS-Block as an infrastructure of analysis tools for TMO to present a point of reference. There is a problem that the existing PS-Block has overhead caused by a policy making duplicated blocks. As such, this paper implements a PS-Block Timing Model to reduce the overhead due to block duplication, and defines a base class for searching in PS-Block. The PS-Block Timing Model, using an improved PS-Block structure, offers a point of reference of deadline and an infrastructure of execution time analysis according to the PS-Block configuration policy. Therefore, TMO developers can easily verify deadline of real-time methods, and improve reliability, and reduce development terms.

• Journal of KIISE:Software and Applications
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• v.29 no.12
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• pp.926-939
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• 2002

The formal specification methods with probability have been demanded in the area of fault real-time systems, in order to specify the uncertainty that the systems can encounter during their execution due to various environmental factors. This paper presents a new formal method with probability. namely Probabilistic Abstract Timed Machine (PATM), in order to analyze and predict system's behavior in dynamical environmental changes, This method classifies the factors into two classes: the variable and the constant. The analysis of system's behavior is performed on the probabilistic reachability graph generated from the ATM specification for the system. The analysis can predict any possibility that the behavior may not satisfy some safety requirements of the system, indicate which variable factors cause such satisfaction, and further recover from this unsatisfying fault state by fixing the variable factors. Consequently the reliability to the fault real-time systems can be improved.

• KNOM Review
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• v.22 no.1
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• pp.60-67
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• 2019

Graphical Processing Units(GPUs) achieve high performance undertaking from relatively uniformed computation in parallel. The technology related to General Purpose GPU(GPGPU) has been enhanced, which provides concurrent kernel execution of multi and diverse applications at the same time, but it is still limited to support resource sharing or planning. NVIDIA recently introduces Multi-Process Service(MPS), which allows kernels from different applications can be execute concurrently. However, the strength of MPS comes along with the characteristics of applications and the order of their execution. This paper shows the performance analysis of diverse scientific applications in real world. Based on the analysis, we prove that it is important to the identify characteristics of co-run applications, and to schedule multiple applications via profiling to maximize MPS functionality.

• Journal of the Korea Convergence Society
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• v.13 no.2
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• pp.249-255
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• 2022

This study proposed an analysis framework for real-time prediction of CNC processing defects using machine learning-based models that are recently attracting attention as processing defect prediction methods, and applied it to CNC machines. Analysis shows that the XGBoost, CatBoost, and LightGBM models have the same best accuracy, precision, recall, F1 score, and AUC, of which the LightGBM model took the shortest execution time. This short run time has practical advantages such as reducing actual system deployment costs, reducing the probability of CNC machine damage due to rapid prediction of defects, and increasing overall CNC machine utilization, confirming that the LightGBM model is the most effective machine learning model for CNC machines with only basic sensors installed. In addition, it was confirmed that classification performance was maximized when an ensemble model consisting of LightGBM, ExtraTrees, k-Nearest Neighbors, and logistic regression models was applied in situations where there are no restrictions on execution time and computing power.

• Journal of Computing Science and Engineering
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• v.8 no.4
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• pp.215-227
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• 2014

In modern computer architectures, caches are widely used to shorten the gap between processor speed and memory access time. However, caches are time-unpredictable, and thus can significantly increase the complexity of worst-case execution time (WCET) analysis, which is crucial for real-time systems. This paper proposes a time-predictable two-level scratchpad-based architecture and an ILP-based static memory objects assignment algorithm to support real-time computing. Moreover, to exploit the load/store latencies that are known statically in this architecture, we study a Scratch-pad Sensitive Scheduling method to further improve the performance. Our experimental results indicate that the performance and energy consumption of the two-level scratchpad-based architecture are superior to the similar cache based architecture for most of the benchmarks we studied.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.1
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• pp.209-221
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• 1999

Several approaches to anlayzing real-time schedulability have been presented, but since these used a fixed priority scheduling scheme and/or traverse all possible state spaces, there take place exponential time and space complexity of these methods. Therefore it is necessary to reduce the state space and detect schedulability at earlier time. This paper proposes and implements an advanced schedulability analysis algorithm to determine that is satisfied a given deadlines for real-time processes. These use a minimum execution time of process, periodic, deadline, and a synchronization time of processes to detect schedulability at earlier time and dynamic scheduling scheme to reduce state space using the transition rules of process algebra. From a result of implementation, we demonstrated the effective performance to determine schedulability analysis.

• Journal of the Korean Society of Industry Convergence
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• v.20 no.1
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• pp.1-7
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• 2017

Most conventional processors execute program instructions in a sequential manner. On the other hand, VLIW processor can execute multiple instructions at the same time. It exploits instruction level parallelism to improve system performance. To that end, program code should be rearranged to VLIW instruction format by a compiler. The compiler determine an optimal execution order of instructions of a program code. This instruction ordering is also called instruction scheduling. The scheduling is an algorithm that decides the execution order for instruction codes in loop parts of a program so that the instruction level parallelism can be maximized. In this research, we apply an existing scheduling algorithm to a VLIW FCC and describe analysis results to further improve its performance. And, we present a solution to solve some limitation of the existing scheduling technique. By using our solution, FCC's performance can be improved upto 32% compared to the existing scheduling only setting.

• KIPS Transactions on Computer and Communication Systems
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• v.4 no.5
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• pp.153-160
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• 2015

The effectiveness of multicores depends on how well a scheduler can assign tasks onto the cores efficiently. In a heterogeneous multicore platform, the execution time of an application depends on which core it executes on. That is to say, the effectiveness of task assignment is one of the important components for a multicore systems' performance. This work proposes a load scheduling technique that analyzes execution time of each task by profiling. The profiling result provides a basic information to predict which task-to-core mapping is likely to provide the best performance. By using such information, the proposed technique is about 26% performance gain.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.21 no.6
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• pp.161-169
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• 2011

Recent intelligent video surveillance system asks for development of more advanced technology for analysis and recognition of video data. Especially, machine learning algorithm such as Support Vector Machine (SVM) is used in order to recognize objects in video. Because SVM training demands massive amount of computation, parallel processing technique is necessary to reduce the execution time effectively. In this paper, we propose a parallel processing method of SVM training with a multi-core processor. The results of parallel SVM on a 4-core processor show that our proposed method can reduce the execution time of the sequential training by a factor of 2.5.