• Proceedings of the Korean Society of Precision Engineering Conference
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• 2003.06a
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• pp.219-222
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• 2003

Self-Assembled Monolayers(SAMs) by alkanethiol adsorption to thin metal film are widely being investigated for applications as coating layer for anti-stiction or friction reduction and in fabrication of micro structure of molecular and bio molecular. Recently, there have been many researches on micro patterning using the advantages of very thin thickness and etching resistance in selective etching of thin metal film of Self- Assembled Monolayers. In this report, we present the micromachining thin metal film by Mask-Less laser patterning of alknanethiolate Self-Assembled Monolayers.

• Transactions on Electrical and Electronic Materials
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• v.7 no.4
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• pp.173-179
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• 2006

Due to the limitations of the channel length, the lateral spread for two-dimensional impurity distributions is critical for the analysis of devices including the integrated complementary metal oxide semiconductor (CMOS) circuits and high frequency semiconductor devices. The developed codes were then compared with the two-dimensional implanted profiles measured by transmission electron microscope (TEM) as well as simulated by a commercial TSUPREM4 for verification purposes. The measured two-dimensional TEM data obtained by chemical etching-method was consistent with the results of the developed analytical model, and it seemed to be more accurate than the results attained by a commercial TSUPREM4. The developed codes can be applied on a wider energy range $(1KeV{\sim}30MeV)$ than a commercial TSUPREM4 of which the maximum energy range cannot exceed 1MeV for the limited doping elements. Moreover, it is not only limited to diffusion process but also can be applied to implantation due to the sloped and nano scale structure of the mask.

• Transactions of Materials Processing
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• v.13 no.4
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• pp.326-333
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• 2004

The nanoprobe based on lithography, mainly represented by SPM based technologies, has been recognized as a potential application to fabricate the surface nanosctructures because of its operational versatility and simplicity. However, nanoprobe based on lithography itself is not suitable for mass production because it is time a consuming method and not economical for commercial applications. One solution is to fabricate a mold that will be used for mass production processes such as nanoimprint, PDMS casting, and others. The objective of this study is to fabricate the silicon stamper for PDMS casting process by a mastless fabrication technique using the combination of nano/micro machining by Nanoindenter XP and KOH wet etching. Effect of the Berkovich tip alignment on the deformation was investigated. Grooves were machined on a silicon surface, which has native oxide on it, by constant load scratch (CLS), and they were etched in KOH solutions to investigate chemical characteristics of the machined silicon surface. After the etching process, the convex structures was made because of the etch mask effect of the mechanically affected layer generated by nanoscratch. On the basis of this fact, some line patterns with convex structures were fabricated. Achieved groove and convex structures were used as a stamper for PDMS casting process.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.6
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• pp.451-455
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• 1999

The highest etch rate of Pt film was obtained at 10% $Cl_2$/90% Ar gas mixing ratio in our previous investigation. However, the problems such as the etch residues(fence) remained on the pattern sidewall, low selectivity to oxide as mask and low etch slope were presented. In this paper, the etching by additive $O_2$ gas to 10% $Cl_2$/90% Ar gas base was examined. As a result, the fence-free pattern and higher etch slope as about 60$^{\circ}$was observed and the selectivity to oxide increased to 2.4 without decreasing of the etch rate $1500{\AA}$/min. XPS surface analysis proved that a only little $O_2$ gas removes the Pt-CI compounds as residues on the etched surface.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.102-102
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• 2008

Sapphire (${\alpha}-Al_2O_3$) has been used as the substrate of opto-electronic device because of characteristics of thermal stability, comparatively low cost, large diameter, optical transparency and chemical compatibility. However, there is difficulty in the etching and patterning due to the physical stability of sapphire and the selectivity with sapphire and mask materials [1,2]. Therefore, sapphire has been studied on the various fields and need to be studied, continuously. In this study, the etching properties of sapphire substrate were investigated with various $CH_4$/Ar gas combination, radio frequency (RF) power, DC-bias voltage and process pressure. The characteristics of the plasma were estimated for mechanism using optical emission spectroscopy (OES). The chemical compounds on the surface of sapphire substrate were investigated using energy dispersive X-ray (EDX). The chemical reaction on the surface of the etched sapphire substrate was observed by X-ray photoelectron spectroscopy (XPS). Scanning electron microscopy (SEM) was used to investigate the vertical and slope profiles.

• Journal of the Semiconductor & Display Technology
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• v.8 no.4
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• pp.49-52
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• 2009

We have investigated the effect of the surface roughness of TCO substrate on the characteristics of OLED (organic light emitting diodes) devices. In order to control the surface roughness of ITO thin films, we have processed photolithography and reactive ion etching. The micro-size patterned mask was used, and the etching depth was controlled by changing etching time. The surface morphology of the ITO thin film was observed by FESEM and atomic force microscopy (AFM). And then, organic materials and cathode electrode were sequentially deposited on the ITO thin films. Device structure was ITO/$\alpha$-NPD/DPVB/Alq3/LiF/Al. The DPVB was used as a blue emitting material. The electrical characteristics such as current density vs. voltage and luminescence vs. voltage of OLED devices were measured by using spectrometer (minolta CS-1000A). The current vs. voltage and luminance vs. voltage characteristics were systematically degraded with increasing surface roughness. Furthermore, the retention test clearly presented that the reliability of OLED devices was directly influenced with the surface roughness, which could be interpreted in terms of the concentration of the electric field on the weak and thin organic layers caused by the poor step coverage.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2005.05a
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• pp.395-400
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• 2005

Nano-scale fabrication of silicon substrate based on the use of atomic force microscopy (AFM) was demonstrated. A specially designed cantilever with diamond tip, allowing the formation of damaged layer on silicon substrate by a simple scratching process, has been applied instead of conventional silicon cantilever for scanning. A thin damaged layer forms in the substrate at the diamond tip-sample junction along scanning path of the tip. The damaged layer withstands against wet chemical etching in aqueous KOH solution. Diamond tip acts as a patterning tool like mask film for lithography process. Hence these sequential processes, called tribo-nanolithography, TNL, can fabricate 2D or 3D micro structures in nanometer range. This study demonstrates the novel fabrication processes of the micro cantilever and diamond tip as a tool for TNL using micro-patterning, wet chemical etching and CVD. The developed TNL tools show outstanding machinability against single crystal silicon wafer. Hence, they are expected to have a possibility for industrial applications as a micro-to-nano machining tool.

• Journal of the Semiconductor & Display Technology
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• v.9 no.4
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• pp.25-29
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• 2010

We have investigated the effect of surface roughness of TCO substrate on the characteristics of OLED (organic light emitting diodes) devices. In order to control the surface roughness of AZO thin films, we have processed photo-lithography and reactive ion etching. The micro-size patterned mask was used, and the etching depth was controlled by changing etching time. The surface morphology of the AZO thin film was observed by FESEM and atomic force microscopy (AFM). And then, organic materials and cathode electrode were sequentially deposited on the AZO thin films. Device structure was AZO/${\alpha}$-NPD/DPVB/$Alq_3$/LiF/Al. The DPVB was used as a blue emitting material. The electrical characteristics such as current density vs. voltage and luminescence vs. voltage of OLED devices were measured by using spectrometer. The current vs. voltage and luminance vs. voltage characteristics were systematically degraded with increasing surface roughness. Furthermore, the retention test clearly presented that the reliability of OLED devices was directly influenced with the surface roughness, which could be interpreted in terms of the concentration of the electric field on the weak and thin organic layers caused by the poor step coverage.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.90.2-90.2
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• 2013

Vertically-aligned silicon nanostructure arrays (SNAs) have been drawing much attention due to their useful electrical properties, large surface area, and quantum confinement effect. SNAs are typically fabricated by chemical vapor deposition, reactive ion etching, or wet chemical etching. Recently, metal-assisted chemical etching process, which is relatively simple and cost-effective, in combination with nanosphere lithography was recently demonstrated for vertical SNA fabrication with controlled SNA diameters, lengths, and densities. However, this method exhibits limitations in terms of large-area preparation of unperiodic nanostructures and SNA geometry tuning independent of inter-structure separation. In this work, we introduced the layerby- layer deposition of polyelectrolytes for holding uniformly dispersed polystyrene beads as mask and demonstrated the fabrication of well-dispersed vertical SNAs with controlled geometric parameters on large substrates. Additionally, we present a new means of building in vitro neuronal networks using vertical nanowire arrays. Primary culture of rat hippocampal neurons were deposited on the bare and conducting polymer-coated SNAs and maintained for several weeks while their viability remains for several weeks. Combined with the recently-developed transfection method via nanowire internalization, the patterned vertical nanostructures will contribute to understanding how synaptic connectivity and site-specific perturbation will affect global neuronal network function in an extant in vitro neuronal circuit.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.241-241
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• 2008

Macrofore formation in silicon and other semiconductors using electrochemical etching processes has been, in the last years, a subject of great attention of both theory and practice. Its first reason of concern is new areas of macropore silicone applications arising from microelectromechanical systems processing (MEMS), membrane techniques, solar cells, sensors, photonic crystals, and new technologies like a silicon-on-nothing (SON) technology. Its formation mechanism with a rich variety of controllable microstructures and their many potential applications have been studied extensively recently. Porous silicon is formed by anodic etching of crystalline silicon in hydrofluoric acid. During the etching process holes are required to enable the dissolution of the silicon anode. For p-type silicon, holes are the majority charge carriers, therefore porous silicon can be formed under the action of a positive bias on the silicon anode. For n-type silicon, holes to dissolve silicon is supplied by illuminating n-type silicon with above-band-gap light which allows sufficient generation of holes. To make a desired three-dimensional nano- or micro-structures, pre-structuring the masked surface in KOH solution to form a periodic array of etch pits before electrochemical etching. Due to enhanced electric field, the holes are efficiently collected at the pore tips for etching. The depletion of holes in the space charge region prevents silicon dissolution at the sidewalls, enabling anisotropic etching for the trenches. This is correct theoretical explanation for n-type Si etching. However, there are a few experimental repors in p-type silicon, while a number of theoretical models have been worked out to explain experimental dependence observed. To perform ordered macrofore formaion for p-type silicon, various kinds of mask patterns to make initial KOH etch pits were used. In order to understand the roles played by the kinds of etching solution in the formation of pillar arrays, we have undertaken a systematic study of the solvent effects in mixtures of HF, N-dimethylformamide (DMF), iso-propanol, and mixtures of HF with water on the macrofore structure formation on monocrystalline p-type silicon with a resistivity varying between 10 ~ 0.01 $\Omega$ cm. The etching solution including the iso-propanol produced a best three dimensional pillar structures. The experimental results are discussed on the base of Lehmann's comprehensive model based on SCR width.