• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.3
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• pp.87-92
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• 1997

Inductively coupled Cl$_{2}$ plasma has been studied to etch Pt thin films, which hardly form volatile compound with any reactive gas at normal process temperature. Low etch rate and residue problems are frequently observed. For higher etch rate, high density plasma and higher process temperature is adopted observed. For higher etch rate, high density plasma and higher process temperature is adopted and thus SiO$_{2}$ is used as for patterning mask instead of photoresist. The effect of O$_{2}$ or Ar addition to Cl$_{2}$ was investigated, and the chamber pressure, gas flow rate, surce RF power and bias RF power are also varied to check their effects on etch rate and selectivity. The major etching mechanism is the physical sputtering, but the ion assisted chemical raction is also found to be a big factor. The proposs can be optimized to obtain the etch rate of Pt up to 200nm/min and selectivity to SiO$_{2}$ at 2.0 or more. Patterning of submicron Pt lines are successfully demonstrated.

• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.860-863
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• 2002

In this study, Ag thin films deposited on LCD-grade glass were etched using inductively coupled fluorine-based plasmas and the effect of various $CF_4$-based gas mixtures on the Ag etching characteristics were studied. When $CF_4$-based gas mixtures were used with $N_2$, due to the very low vapor pressure of etch products, etch products remained on the substrate after the etching. However, when $CF_4$ used with Ar, residue-free Ag etching could be obtained due to the removal of etch product by sputtering by $Ar^+$ ions.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1408-1411
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• 2009

This paper describes organic acid-based wet chemical etching behaviors of amorphous Ga-doped zinc oxide (GZO) thin film sputter-deposited at low temperature (room temperature). Wet etch parameters such as etching time, temperature, and etchant concentration are investigated for formic and citric acid etchants, and their effects on the etch rate, etch residue and the feature of edge line are compared.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.4
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• pp.286-291
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• 2003

(Pb,Sr)TiO$_3$(PST) thin films have attracted great interest as new dielectric materials of capacitors for Gbit dynamic random access memories. In this study, inductively coupled CF$_4$/Ar plasma was used to etch PST thin films. The maximum etch rate of PST thin films was 740 $\AA$/min at a CF$_4$(20 %)/Ar(80 %) 9as mixing ratio, an RF power of 800 W, a DC bias voltage of -200 V, a total gas flow of 20 sccm, and a chamber pressure of 15 mTorr. To clarify the etching mechanism, the residue on the surface of the etched PST thin films was investigated by X-ray photoelectron spectroscopy. It was found that Pb was mainly removed by physically assisted chemical etching. Sputter etching was effective in the etching of Sr than the chemical reaction of F with Sr, while Ti can almost removed by chemical reaction.

• Proceedings of the Materials Research Society of Korea Conference
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• 1993.05a
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• pp.45-45
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• 1993

• Journal of the Korean Vacuum Society
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• v.6 no.4
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• pp.364-371
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• 1997

Silicon trench etching has been carried out using a magnetically enhanced reactive ion etching system in HBr plasma containing He-$O_2$, $CF_4$. The changes of etch rate and etch profile, the degree of residue formation, and the change of surface chemical state were investigated as a function of additive gas flow rate. A severe lateral etching was observed when pure HBr plasma was used to etch the silicon, resulted in a pot shaped trench. When He-$O_2$, $SiF_4$ additives were added to HBr plasma, the lateral etching was almost eliminated and a better trench etch profile was obtained. The surface etched in HBr/He-$O_2/SiF_4$ plasma showed relatively low contamination and residue elements compared to the surface etched in HBr/He-$O-2/CF_4$plasma. In addition, the etching characteristics including low residue formation and chemically clean etched surface were obtained by using HBr containing He-$O_2$ or $SiF_4$ additive gases instead of $CF_4$ gas, which were confirmed by X-ray photoelectron spectroscopy (XPS), scanning electron microscopy (SEM) and atomic force microscopy (AFM).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.1
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• pp.1-5
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• 2001

STI(shallow trench isolation)-CMP(chemical mechanical polishing) process have been substituted for LOCOS(local oxidation of silicon) process to obtain global planarization in the below sub-0.5㎛ technology. However TI-CMP process, especially TI-CMP with RIE(reactive ion etching) etch back process, has some kinds of defect like nitride residue, torn oxide defect, etc. In this paper, we studied how to reduced torn oxide defects after STI-CMP with RIE etch back processed. Although torn oxide defects which can occur on trench area is not deep and not severe, torn oxide defects on moat area is not deep and not severe, torn oxide defects on moat area is sometimes very deep and makes the yield loss. Thus, we did test on pattern wafers which go through trench process, APECVD process, and RIE etch back process by using an IPEC 472 polisher, IC1000/SUVA4 PAD and KOH base slurry to reduce the number of torn defects and to study what is the origin of torn oxide defects.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.12
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• pp.996-1002
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• 2000

Ferroelectric (Ba, Sr) TiO$_3$(BST) thin films have attracted much attention for use in new capacitor materials of dynamic random access memories (DRAMs). In order to apply BST to the DRAMs, the etching process for BST thin film with high etch rate and vertical profile must be developed. However, the former studies have the problem of low etch rate. In this study, in order to increase the etch rate, BST thin films were etched with a magnetically enhanced inductively coupled plasma(MEICP) that have much higher plasma density than RIE (reactive ion etching) and ICP (inductively coupled plasma). Experiment was done by varying the etching parameters such as CF$_4$/(CF$_4$+Ar) gas mixing ratio, rf power, dc bias voltage and chamber pressure. The maximum etch rate of the BST films was 170nm/min under CF$_4$/CF$_4$+Ar) of 0.1, 600 W/-350 V and 5 mTorr. The selectivities of BST to Pt and PR were 0.6 and 0.7, respectively. Chemical reaction and residue of the etched surface were investigated with X-ray photoelectron spectroscopy (XPS) and secondary ion mass spectroscopy (SIMS).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.747-750
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• 2007

This study proposes that chlorine residue after metal etch as the source of metal corrosion, and charges should be removed by optimizing etch, PR strip and cleaning condition. Charges distributed along the metal line acts as a source of tungsten (W) plug corrosion when associated with following cleaning solution. In cleaning process after metal etch and PR strip, chemical selection is significantly important in terms of metal corrosion. Optimal corrosion preventive PH, no metal attack (choice of optimal inhibitants), high by product removal efficiency and optimal de ionized water treatment condition is critical to the metal corrosion prevention.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.88-89
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• 2009

In this paper, we investigated about wet cleaning effect as deep trench formation methods for Power chip devices. Deep trench structure was classified by two methods, PSU (Poly Stick Up) and Non-PSU structure. In this paper, we could remove residue defect during wet. cleaning after deep trench etch process for non-PSU structure device as to change wet cleaning process condition. V-SEM result showed void image at the trench bottom site due to residue defect and residue component was oxide by EDS analysis. In order to find the reason of happening residue defect, we experimented about various process conditions. So, defect source was that oxide film was re-deposited at trench bottom by changed to hydrophobic property at substrate during hard mask removal process. Therefore, in order to removal residue defect, we added in-situ SCI during hard mask removal process, and defect was removed perfectly. And WLR (Wafer Level Reliability) test result was no difference between normal and optimized process condition.