• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.10
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• pp.1495-1507
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• 1993

In this paper, an implementation of RS (Reed-Solomon) code decoder for CDP (Compact Disc Player) using microprogramming method is presented. In this decoding strategy, the equations composed of Newton's identities are used for computing the coefficients of the error locator polynomial and for checking the number of erasures in C2(outer code). Also, in C2 decoding the values of erasures are computed from syndromes and the results of C1(inner code) decoding. We pulled up the error correctability by correcting 4 erasures or less. The decoder contains an arithmetic logic unit over GF(28) for error correcting and a decoding controller with programming ROM, and also microinstructions. Microinstructions are used for an implementation of a decoding algorithm for RS code. As a result, it can be easily modified for upgrade or other applications by changing the programming ROM only. The decoder is implemented by the Logic Level Modeling of Verilog HDL. In the decoder, each microinstruction has 14 bits( = 1 word), and the size of the programming ROM is 360 words. The number of the maximum clock-cycle for decoding both C1 and C2 is 424.

• Journal of Electrical Engineering and information Science
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• v.1 no.1
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• pp.17-22
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• 1996

Adaptive code rate change schemes in DS-SSMA systems are proposed. In the proposed schemes, the error correcting code rate is changed according to the channel states. Two channel states having significant effects on the bit error probability are considered: one is the effective number of users, and the other is the fading environment. These channel states are estimated based on retransmission requests. The criterion for the change of the code rate is to maximize the throughput under given error bound.

• International Journal of Advanced Culture Technology
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• v.9 no.1
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• pp.203-209
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• 2021

When carrying out computer programming, the process of checking and correcting errors in the source code is essential work for the completion of the program. Non-computer majors who are learning programming for the first time receive feedback from instructors to correct errors that occur when writing the source code. However, in a learning environment where the time for the learner to practice alone is long, such as an online learning environment, the learner starts to feel many difficulties in solving program errors by himself/herself. Therefore, training on how to check and correct errors after writing the program source code is necessary. In this paper, various types of errors that can occur in a Python program were described, the errors were classified into simple errors and complex errors according to the characteristics of the errors, and the distributions of errors by Python grammar category were analyzed. In addition, a coding learning process to refer error lists was designed to present a coding learning method that enables learners to solve program errors by themselves.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.5
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• pp.24-28
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• 1985

In this paper, the cyclic product codes which are capable of correcting random erros and burst errors simultaneously have been designed and constructed. First, the procedure for product of two cyclic codes is shown and thin the encoder and decoder system using the (7,4) cyclic Hamming code and the (3,1) cyclic code is implemented. The micro-computer is used for experiment and the system consists of encoder, decoder and interface circuits. The encoder of cyclic product code is implemented by interlacing encoders while the decoder is implemented by cascading decoders that interlace error trapping decoders. In conclusion, cyclic product codas are easily decodable and are capable of correcting four random errors and eight-burst errors. Better performance is obtained with low error rate.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.1
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• pp.59-66
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• 1998

In this paper, the high-speed decoder for RS(Reed-Solomon) code, one of the most popular error correcting code, is implemented using VHDL. This RS decoder is designed in transform domain instead of most time domain. Because of the simplicity in structure, transform decoder can be easily realized VLSI chip. Additionally the pipeline architecture, which is similar to a systolic array is applied for all design. Therefore, This transform RS decoder is suitable for high-rate data transfer. After synthesis with FPGA technology, the decoding rate is more 43 Mbytes/s and the area is 1853 LCs(Logic Cells). To compare with other product with pipeline architecture, this result is admirable. Error correcting ability and pipeline performance is certified by computer simulation.

• Nuclear Engineering and Technology
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• v.50 no.8
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• pp.1306-1313
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• 2018

The randomness and incipient nature of certain faults in reactor systems warrant a robust and dynamic detection mechanism. Existing models and methods for fault diagnosis using different mathematical/statistical inferences lack incipient and novel faults detection capability. To this end, we propose a fault diagnosis method that utilizes the flexibility of data-driven Support Vector Machine (SVM) for component-level fault diagnosis. The technique integrates separately-built, separately-trained, specialized SVM modules capable of component-level fault diagnosis into a coherent intelligent system, with each SVM module monitoring sub-units of the reactor coolant system. To evaluate the model, marginal faults selected from the failure mode and effect analysis (FMEA) are simulated in the steam generator and pressure boundary of the Chinese CNP300 PWR (Qinshan I NPP) reactor coolant system, using a best-estimate thermal-hydraulic code, RELAP5/SCDAP Mod4.0. Multiclass SVM model is trained with component level parameters that represent the steady state and selected faults in the components. For optimization purposes, we considered and compared the performances of different multiclass models in MATLAB, using different coding matrices, as well as different kernel functions on the representative data derived from the simulation of Qinshan I NPP. An optimum predictive model - the Error Correcting Output Code (ECOC) with TenaryComplete coding matrix - was obtained from experiments, and utilized to diagnose the incipient faults. Some of the important diagnostic results and heuristic model evaluation methods are presented in this paper.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.10C
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• pp.605-613
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• 2011

In most digital communication systems over the noisy channel, some form of forward error correction scheme is employed for reliable communications. If one wants to recover the transmitted message without any knowledge of the error correcting codes employed, it is of utmost importance to figure out and reconstruct the error correcting codes. In this paper, we propose two algorithms of reconstructing linear cyclic codes from the corrupted received bit sequence, one for general linear binary cyclic codes and the other for Reed-Solomon codes. For two algorithms, we ran computer simulations and the performances are shown to be superior to those with the conventional LWM method.

• IEMEK Journal of Embedded Systems and Applications
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• v.4 no.4
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• pp.195-200
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• 2009

As 4G mobile communication systems require high transmission rates with reliability, the need for efficient error correcting code is increasing. In this paper, a novel LDPC (Low Density Parity Check) decoder is introduced. The LDPC code is one of the most popular error correcting codes. In order to improve performance of the LDPC decoder, we use SNR (Signal-to-Noise Ratio) estimation results to adjust coefficients of modified UMP-BP (Uniformly Most Probable Belief Propagation) algorithm which is one of widely-used LDPC decoding algorithms. An advantage of Modified UMP-BP is that it is amenable to implement in hardware. We generate the optimal values by simulation for various SNRs and coefficients, and the values are stored in a look-up table. The proposed decoder decides coefficients of the modified UMP-BP based on SNR information. The simulation results show that the BER (Bit Error Rate) performance of the proposed LDPC decoder is better than an LDPC decoder using a conventional modified UMP-BP.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.3
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• pp.226-231
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• 2010

This paper proposes a new coding technique for constructing error correcting high rate DC-free multimode code using a generator matrix generated from a sparse parity-check matrix. The scheme exploits high rate generator matrixes for producing distinct candidate codewords. The decoding complexity depends on whether the syndrome of the received codeword is zero or not. If the syndrome is zero, the decoding is simply performed by expurgating the redundant bits of the received codeword. Otherwise, the decoding is performed by a sum-product algorithm. The performance of the proposed scheme can achieve a reasonable DC-suppression and a low bit error rate.

• Journal of Information Processing Systems
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• v.15 no.6
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• pp.1438-1448
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• 2019

We present a new technique, called VED (very effective debugging), for detecting and correcting division by zero errors for all types of .NET application. We use applications written in C# because C# applications are distributed through the internet and its executable format is used extensively. A tool called Immunity Debugger is used to reverse engineer executable code to get binaries of source code. With this technique, we demonstrate integer division by zero errors, the location of the error causing assembly language code, as well as error recovery done according to user preference. This technique can be extended to work for other programming languages in addition to C#. VED can work on different platforms such as Linux. This technique is simple to implement and economical because all the software used here are open source. Our aims are to simplify the maintenance process and to reduce the cost of the software development life cycle.