• Title/Summary/Keyword: engineered pattern

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Crack initiation mechanism and meso-crack evolution of pre-fabricated cracked sandstone specimens under uniaxial loading

  • Bing Sun;Haowei Yang;Sheng Zeng;Yu Yin;Junwei Fan
    • Geomechanics and Engineering
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    • 재33권6호
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    • pp.597-609
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    • 2023
  • The instability and failure of engineered rock masses are influenced by crack initiation and propagation. Uniaxial compression and acoustic emission (AE) experiments were conducted on cracked sandstone. The effect of the crack's dip on the crack initiation was investigated using fracture mechanics. The crack propagation was investigated based on stress-strain curves, AE multi-parameter characteristics, and failure modes. The results show that the crack initiation occurs at the tip of the pre-fabricated crack, and the crack initiation angle increases from 0° to 70° as the dip angle increases from 0° to 90°. The fracture strength kcr is derived varies in a U-shaped pattern as β increased, and the superior crack angle βm is between 36.2 and 36.6 and is influenced by the properties of the rock and the crack surface. Low-strength, large-scale tensile cracks form during the crack initiation in the cracked sandstone, corresponding to the start of the AE energy, the first decrease in the b-value, and a low r-value. When macroscopic surface cracks form in the cracked sandstone, high-strength, large-scale shear cracks form, resulting in a rapid increase in the AE energy, a second decrease in the b-value and an abrupt increase in the r-value. This research has significant theoretical implications for rock failure mechanisms and establishment of damage indicators in underground engineering.

Fabrication and characterization of $WSi_2$ nanocrystals memory device with $SiO_2$ / $HfO_2$ / $Al_2O_3$ tunnel layer

  • Lee, Hyo-Jun;Lee, Dong-Uk;Kim, Eun-Kyu;Son, Jung-Woo;Cho, Won-Ju
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2011년도 제40회 동계학술대회 초록집
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    • pp.134-134
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    • 2011
  • High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

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