• Journal of Broadcast Engineering
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• v.21 no.4
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• pp.578-591
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• 2016

In this paper, the fast encoding algorithm in High Efficiency Video Coding (HEVC) encoder was studied. For the encoding efficiency, the current HEVC reference software is divided the input image into Coding Tree Unit (CTU). then, it should be re-divided into CU up to maximum depth in form of quad-tree for RDO (Rate-Distortion Optimization) in encoding precess. But, it is one of the reason why complexity is high in the encoding precess. In this paper, to reduce the high complexity in the encoding process, it proposed the method by determining the maximum depth of the CU using a hierarchical clustering at the pre-processing. The hierarchical clustering results represented an average combination of motion vectors (MV) on neighboring blocks. Experimental results showed that the proposed method could achieve an average of 16% time saving with minimal BD-rate loss at 1080p video resolution. When combined the previous fast algorithm, the proposed method could achieve an average 45.13% time saving with 1.84% BD-rate loss.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.8C
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• pp.720-728
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• 2007

For the improvement of coding efficiency, the H.264/AVC video coding standard employs new coding tools compared with existing coding standards. However, due to these new coding tools, the complexity of H.2641AVC encoder is greatly increased. Specially, Inter/Intra mode decision method of H.264/AVC using RDO(rate-distortion optimization) technique is one of the most complex parts in H.264/AVC. In this paper, we focus on the complexity reduction in macroblock mode decision considering coding efficiency. From the simulation results, the proposed algorithm reduce the encoding time by maximum 80% of total, and reduce the bitrate of the overall sequences by $8{\sim}10%$ on the average compared with existing coding methods.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.6C
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• pp.842-847
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• 2004

We present a new video coding technique to tradeoff frame rate and picture quality for low bit rate video coding. We show a model equation for selecting the optimal frame rate from the motion content of the source video. We can determine DCT quantization parameter (QP) using the frame rate and bit rate. For objective video quality measurement we propose a simple and effective error measure for skipped frames. The proposed method enhances the video quality up to 2 ㏈ over the H.263 TMN5 encoder.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.9C
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• pp.913-921
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• 2007

Retargetable compiler which generates executable code for a target processor and performance profiler are required to design a processor optimized for a specific application. This paper presents an architecture exploration methodology based on ADL (Architecture Description Language). We synthesized instruction set and optimized processor structure using information extracted from application program. The information of operation sequences executed frequently and register usage are used for processor optimization. Architecture exploration has been performed for JPEG encoder to show the effectiveness of the system. The ASIP designed using the proposed method shows 1.97 times better performance.

• ETRI Journal
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• v.39 no.4
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• pp.582-591
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• 2017

To address the wire complexity problem in large-scale globally asynchronous, locally synchronous systems, a current-mode ternary encoding scheme was devised for a two-phase asynchronous protocol. However, for data transmission through a very long wire, few studies have been conducted on reducing the long propagation delay in current-mode circuits. Hence, this paper proposes a current steering logic (CSL) that is able to minimize the long delay for the devised current-mode ternary encoding scheme. The CSL creates pulse signals that charge or discharge the output signal in advance for a short period of time, and as a result, helps prevent a slack in the current signals. The encoder and decoder circuits employing the CSL are implemented using $0.25-{\mu}m$ CMOS technology. The results of an HSPICE simulation show that the normal and optimal mode operations of the CSL achieve a delay reduction of 11.8% and 28.1%, respectively, when compared to the original scheme for a 10-mm wire. They also reduce the power-delay product by 9.6% and 22.5%, respectively, at a data rate of 100 Mb/s for the same wire length.

• Journal of Advanced Navigation Technology
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• v.13 no.4
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• pp.523-531
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• 2009

In this study, we propose a joint source/channel rate control algorithm for video encoder targeting packet erasure channel. Based on the buffer constraints of video communication systems, encoding rate constraint is presented. After defining source distortion models for coded and skipped video frames and a channel distortion model for packet errors and their propagation, an average distortion model of received video is proposed for a given encoding window. Finally, we define an optimization problem to minimize the average distortion for given channel rates and packet loss rates by controlling spatio-temporal parameters of source video and FEC block sizes. Then, we propose a window-based algorithm to solve the problem in real-time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.3C
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• pp.269-277
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• 2007

In this paper, we present a efficient transcoding method from MPEG-2 to H.264. The proposed transcoder is the transcoding method for spatial domain which consists of MPEG-2 decoder part and H.264 encoding part. In transcoder, we can get useful information to estimate less probable modes from MPEG-2 decoder. Using this information, H.264 encoder chooses the macroblock mode of I-frame and P-frame adaptively to reduce the whole complexity of the transcoder. Our experimental result shows that the proposed algorithm can archive about $30\sim60%$ computational saving without significant degradation of visual quality and increasing of bit rate.

• Journal of information and communication convergence engineering
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• v.7 no.2
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• pp.193-198
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• 2009

The H.264/ AVC video coding standard supports the intra prediction with various block sizes for luma component and a 8x8 block size for chroma components. This new feature of H.264/AVC offers a considerably higher improvement in coding efficiency compared to previous compression standards. In order to achieve this, H.264/AVC uses the Rate-distortion optimization (RDO) technique to select the best intra prediction mode for each block size, and it brings about the drastic increase of the computation complexity of H.264 encoder. In this paper, a fast block size decision algorithm is proposed to reduce the computation complexity of the intra prediction in H.264/AVC. The proposed algorithm computes the smoothness based on AC and DC coefficient energy for macroblocks and compares with the nonparametric criteria which is determined by considering information on neighbor blocks already reconstructed, so that deciding the best probable block size for the intra prediction. Also, the use of non-parametric criteria makes the performance of intra-coding not be dependent on types of video sequences. The experimental results show that the proposed algorithm is able to reduce up to 30% of the whole encoding time with a negligible loss in PSNR and bitrates and provides the stable performance regardless types of video sequences.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.332-335
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• 2007

A real-time frame-layer rate control algorithm with a transmission buffer is proposed for minimizing video quality variation. The proposed rate control method uses a non-iterative optimization method for low computational complexity, and performs bit allocation at the frame level to minimize variation in distortion between frames. In order to reflect the buffer status, we use well-known PID control method. Computational complexity of PID control is very low, so the proposed algorithm is suitable for real-time low-complexity video encoder. Experimental results indicate that the proposed control method provides better PSNR performance than the existing rate control method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.8
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• pp.2003-2012
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• 1996

The 16- and 32-state Trellis-coded M-ary 4-dimensional (4-D) orthogonal modulation scheme with a frequency-reuse technique have been investigated. Here, 5 coded bits form a rate 4/5 convolutional encoder provide 32 possible symbols. Then the signals are mapped by a M-ary 4-D orthogonal modulator, where each signal has equal energy and is PSK modulated. In the M-ary 4-D modulator, we have employed the vectors which is derived by the optimization technique of signal waveforms in a 4-D sphere. This technique is usedin maximizing the minimum Euclidean distance between a set of signal poits on a multidimensional sphere. By combinig trellis coding with M-ary 4-D modulation and proper set-partitioning, we have obtained a considerable impeovement in the free minimum distance of the system over an AWGN channel. The 16-state scheme obtains coding gains up to 5.5 dB over the uncoded two-independent QPSK scheme and 2.5 dB over the two-independent 2-D TCM scheme. And, the 32-state scheme obtains coding gains up to 6.4 dB over the uncoded two-independent QPSK schemeand 3.4 dB over the two-independent 2-D TCM scheme.