• Korean Journal of Optics and Photonics
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• v.17 no.3
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• pp.273-277
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• 2006

In this paper, we constructed the Littman type and fixed Littrow type tunable external-cavity diode laser systems. The laser output, which is the 0th-order diffracted beam from the diffraction grating in an external cavity, was the single longitudinal mode. Its FWHM was measured as less than 9MHz. With the diode driving current of 140mA and operating temperature of $25^{\circ}C$, the coarse tuning range of 5.375nm was measured for the Littman type, and of 13.65nm was measured for the fixed Littrow type. A fine tuning experiment in which an external mirror was rotated by a PZT driven by a sawtooth wave was performed, and its tuning range of 0.042nm was measured for both types. The fixed Littrow type tunable external-cavity diode laser system was an improvement on the conventional Littrow type tunable laser system in which the output direction varies due to the grating embedded in the mirror plate.

• The Journal of the Korea Contents Association
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• v.12 no.6
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• pp.68-77
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• 2012

As the system development environment moves from single core to multi core-based platforms, it becomes more important to maintain compatibility between single core-based implementations and multi core-based implementations. Moreover, it is very important to support real-time on multi core platforms especially in cases of embedded software or test equipments which need real-time as well as correctness. Since Windows operating system dopes not support real-time in itself, it has been supporting real-time using expensive third-party solutions such as RTX or INtime. So as to reduce this kind of development expenses, in this paper, we propose RTiK-MP(Real-Time implant Kernel-Multi Processor) which supports real-time on Windows using the Local APIC of x86 architectures, and evaluate the performance of the proposed RTiK-MP after deploying it on portable missile test equipments.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.11
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• pp.1477-1483
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• 2020

The stability guarantee of wireless network based control systems is still challenging due to the lossy links and node failures. This paper proposes a hierarchical cluster-based network protocol called robust wireless sensor and actuator network (R-WSAN) by combining time, channel, and space resource diversity. R-WSAN includes a scheduling algorithm to support the network resource allocation and a control task sharing scheme to maintain the control stability of multiple plants. R-WSAN was implemented on a real test-bed using Zolertia RE-Mote embedded hardware platform running the Contiki-NG operating system. Our experimental results demonstrate that R-WSAN provides highly reliable and robust performance against lossy links and node failures. Furthermore, the proposed scheduling algorithm and the task sharing scheme meet the stability requirement of control systems, even if the controller fails to support the control task.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.34 no.3
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• pp.365-378
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• 2024

The operating system (OS) of mobiles or embedded devices is based on the Linux kernel. These OSs request random numbers from the Linux kernel for system operation, such as encryption keys and security features. To provide random numbers reliably, the Linux kernel has a dedicated random number generator (Linux Pseudo Random Number Generator, LPRNG). Recently, LPRNG has undergone a major structural changes. However, despite the major changes, no security analysis has been published on the structure of the new LPRNG. Therefore, we analyze these structural changes as a preliminary study to utilize the security analysis of the new LPRNG. Furthermore, the differences between before and after the changes are divided into cryptographic and performance perspectives to identify elements that require security analysis. This result will help us understand the new LPRNG and serve as a base for security analysis.

• Nuclear Engineering and Technology
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• v.56 no.9
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• pp.3700-3716
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• 2024

Owing to spatial effects and vortex flow, flow in research reactors that use plate-type fuels can be maldistributed to the parallel channels of the core, which significantly impacts the reactor safety. In this study, the core flow of an advanced research reactor was measured in a real-scale facility under various hydraulic conditions. For flow measurement, integrated pressure lines were embedded in the mockups of 22 fuel assemblies and six fission molybdenum assemblies. Each assembly mockup was individually calibrated to obtain the relationship between the pressure drop and flow rate. Real-scale facility, which implements the characteristics of the hydraulic conditions in research reactors, was then used to evaluate the assembly-to-assembly flow distribution under normal operating condition, a partially withdrawn condition for the follower fuel assemblies, no flow for the pool water management system, and 1:1.5 asymmetric inlet flow condition. As a parallel channel system, core flow distribution was analyzed with conventional header design approach. Taking into account the measuring uncertainty, the core flow was uniformly distributed within 5 % under all conditions. This was mainly because the core flow resistance was sufficiently high and the vortex flow was minimized by the perforated plate.

• Journal of Software Assessment and Valuation
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• v.16 no.1
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• pp.65-79
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• 2020

As Programmable Logic Controllers (PLCs), popular components in industrial control systems (ICS), are incorporated with the technologies such as micro-controllers, real-time operating systems, and communication capabilities. As the latest PLCs have been connected to the Internet, they are becoming a main target of cyber threats. This paper proposes two sanitizers that improve the security of uC/OS-II based firmware for a PLC. That is, we devise BU sanitizer for detecting out-of-bounds accesses to buffers and UaF sanitizer for fixing use-after-free bugs in the firmware. They can sanitize the binary firmware image generated in a desktop PC before downloading it to the PLC. The BU sanitizer can also detect the violation of control flow integrity using both call graph and symbols of functions in the firmware image. We have implemented the proposed two sanitizers as a prototype system on a PLC running uC/OS-II and demonstrated the effectiveness of them by performing experiments as well as comparing them with the existing sanitizers. These findings can be used to detect and mitigate unintended vulnerabilities during the firmware development phase.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.41 no.10
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• pp.805-812
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• 2013

The operational flight program(OFP) which has the functions of I/O processing with avionics, flight control logic calculation, fault diagnosis and redundancy mode is embedded in the flight control computer of Smart UAV. The OFP was developed in the environment of PowerPC 755 processor and VxWorks 5.5 real-time operating system. The OFP consists of memory access module, device I/O signal processing module and flight control logic module, and each module was designed to hierarchical structure. Memory access and signal processing modules were verified from bench test, and flight control logic module was verified from hardware-in-the-loop simulation(HILS) test, ground integration test, tethered test and flight test. This paper describes development environment, software structure, verification and management method of the OFP.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.254-254
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• 2011

The memories with nano-particles are very attractive because they are promising candidates for low operating voltage, long retention time and fast program/erase speed. In recent, various nano-floating gate memories with metal-oxide nanocrystals embedded in organic and inorganic layers have been reported. Because of the carrier generation in semiconductor, induced photon pulse enhanced the program/erase speed of memory device. We studied photo-induced electrical properties of these metal-oxide nanocrystal memory devices. At first, 2~10-nm-thick Sn and In metals were deposited by using thermal evaporation onto Si wafer including a channel with $n^+$ poly-Si source/drain in which the length and width are 10 ${\mu}m$ each. Then, a poly-amic-acid (PAA) was spin coated on the deposited Sn film. The PAA precursor used in this study was prepared by dissolving biphenyl-tetracarboxylic dianhydride-phenylene diamine (BPDA-PDA) commercial polyamic acid in N-methyl-2-pyrrolidon (NMP). Then the samples were cured at 400$^{\circ}C$ for 1 hour in N atmosphere after drying at 135$^{\circ}C$ for 30 min through rapid thermal annealing. The deposition of aluminum layer with thickness of 200 nm was followed by using a thermal evaporator, and then the gate electrode was defined by photolithography and etching. The electrical properties were measured at room temperature using an HP4156a precision semiconductor parameter analyzer and an Agilent 81101A pulse generator. Also, the optical pulse for the study on photo-induced electrical properties was applied by Xeon lamp light source and a monochromator system.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.6
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• pp.181-186
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• 2015

With the rapid growth of semiconductor technologies, small-sized devices with powerful computing abilities are becoming a reality. As this environment has a limit on power supply, NVM storage that has a high density and low power consumption is preferred to HDD or SSD. However, legacy software layers optimized for HDDs should be revisited. Specifically, as storage performance approaches DRAM performance, existing I/O mechanisms and software configurations should be reassessed. This paper explores the challenges and implications of using NVM storage with a broad range of experiments. We measure the performance of a system with NVM storage emulated by DRAM with proper timing parameters and compare it with that of HDD storage environments under various configurations. Our experimental results show that even with storage as fast as DRAM, the performance gain is not large for read operations as current I/O mechanisms do a good job hiding the slow performance of HDD. To assess the potential benefit of fast storage media, we change various I/O configurations and perform experiments to quantify the effects of existing I/O mechanisms such as buffer caching, read-ahead, synchronous I/O, direct I/O, block I/O, and byte-addressable I/O on systems with NVM storage.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.1
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• pp.1-10
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• 2008

In this paper, we designed a facial feature(eyes, a moult and a nose) detection hardware based on the ICT transform which was developed for face detection earlier. Our design used a pipeline architecture for high throughput and it also tried to reduce memory size and memory access rate. The algerian and its hardware implementation were tested on the BioID database, which is a worldwide face detection test bed, and its facial feature detection rate was 100% both in software and hardware, assuming the face boundary was correctly detected. After synthesizing the hardware on Dongbu $0.18{\mu}m$ CMOS library, its die size was $376,821{\mu}m^2$ with the maximum operating clock 78MHz.