• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.5
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• pp.2741-2761
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• 2017

With the purpose of copyright protection for digital video, a novel H.264/AVC watermarking algorithm based on JND model is proposed. Firstly, according to the characteristics of human visual system, a new and more accurate JND model is proposed to determine watermark embedding strength by considering the luminance masking, contrast masking and spatial frequency sensitivity function. Secondly, a new embedding strategy for H.264/AVC watermarking is proposed based on an analysis on the drift error of energy distribution. We argue that more robustness can be achieved if watermarks are embedded in middle and high components of $4{\times}4$ integer DCT since these components are more stable than dc and low components when drift error occurs. Finally, according to different characteristics of middle and high components, the watermarks are embedded using different algorithms, respectively. Experimental results demonstrate that the proposed watermarking algorithm not only meets the imperceptibility and robustness requirements, but also has a high embedding capacity.

• Journal of Korea Multimedia Society
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• v.10 no.5
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• pp.594-603
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• 2007

This paper proposes a watermarking scheme for 3D CAD design drawing. In the proposed scheme, we embed binary watermarks into line, arc, and polygon face components that are the basic component of 3D CAD design drawing. The embedding target component can be selected randomly among three components or by the component distribution in drawing. In line components, a watermark bit is embedded into the ratio of the length of a target line and an average length of lines that are connected into a target line. Furthermore, a watermark bit is embedded into a curvature radius on the basis of a center point in a arc component and also is embedded into a ratio of two sides in a polygonal face component. Experimental results verified that the proposed watermarking has the robustness against Format conversion, rotation translation, scaling, cropping, and layer cutting and also SNR of watermarked component is about 39.89-42.50 dB.

• IEMEK Journal of Embedded Systems and Applications
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• v.9 no.6
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• pp.307-314
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• 2014

Recently, software reliability and safety issues are seriously considered since failures of embedded systems may cause the damages of human lifes. For verifying and testing embedded software, execution environment including sensors and actuators should be prepared in the actual plants or virtual forms on PC. In this paper, we provide the virtual prototype based code simulation techniques and testing framework on PC. Virtual prototypes are generated by combining the Adobe's Flash SWF images corresponding to the state machine of HW or environment components. Code simulation on PC is possible by replacing the device drivers into virtual drivers which connect to virtual prototypes. Also, testing is performed by controlling the states of virtual prototype and simulators. By using these tools, embedded software can be executed in the earlier development phase and the efficiency and SW quality can be enhanced.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.458-461
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• 2011

IT related services are available in the shipborne and maritime area. As their service requirements are requested diversely, the safe and reliable embedded system based device needs increase. There are two categories in embedded system : communication/control system and various user interface needed service system. In this paper, we propose the classification of embedded system in the shipborne and maritime area and provide two reference embedded system platforms and their components. One is low-level embedded reference platform of communication/control system and the other is high-level embedded reference platform of user interface oriented system.

• IE interfaces
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• v.23 no.1
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• pp.35-47
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• 2010

This paper presents a structured framework for developing the embedded subsystem, called ESDMP (Embedded Subsystem Development Methodology for POP), which is one of core components at the development of POP (Point Of Production) system. It is essential that embedded subsystem development methodology must be closely related to the general information system development methodology from the early stage of system development. Therefore, this paper investigates the PDSM (Production System Development Methodology) that is developed by Korea Technology and Information Promotion Agency for SMEs and widely utilized at the fields of POP system development, and proposes the embedded subsystem development methodology aligned with each step of PSDM. The main characteristics of proposed methodology are as follows : First, it is developed to link each step of embedded subsystem development with relating steps of PSDM from the early stage of feasibility study. Second, it provides the procedure for designing and implementing hardware and software simultaneously. Third, it includes the method of reusability for developed products and modules.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.45-45
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• 2007

Capacitors among the embedded passive components are most widely studied because they are the major components in terms of size and number and hard to embed compared with resistors and inductors due to the more complicated structure. To fabricate a capacitor-embedded PCB for in-line process, it is essential to adopt a low temperature process (<$200^{\circ}C$). However, high dielectric materials such as ferroelectrics show a low permittivity and a high dielectric loss when they are processed at low temperatures. To solve these contradicting problems, we studied BMN materials as a candidate for dielectric capacitors. processed at PCB-compatible temperatures. The morphologies of BMN thin films were investigated by AFM and SEM equipment. The electric properties (C-F, I-V) of Pt/BMN/Cu/polymer were evaluated using an impedance analysis (HP 4194A) and semiconductor parameter analyzer (HP4156A). $Bi_2Mg_{2/3}Nb_{4/3}O_7$(BMN) thin films deposited on copper clad laminate substrates by sputtering system as a function of Ar/$O_2$ flow rate at room temperature showed smooth surface morphologies having root mean square roughness of approximately 5.0 nm. 200-nm-thick films deposited at RT exhibit a dielectric constant of 40, a capacitance density of approximately $150\;nF/cm^2$, and breakdown voltage above 6 V. The crystallinity of the BMN thin films was studied by TEM and XRD. BMN thin film capacitors are expected to be promising candidates as embedded capacitors for printed circuit board (PCB).

• Computers and Concrete
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• v.5 no.4
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• pp.401-416
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• 2008

The paper presents a methodology to model three-dimensional reinforced concrete members by means of embedded discontinuity elements based on the Continuum Strong Discontinuous Approach (CSDA). Mixture theory concepts are used to model reinforced concrete as a 3D composite material constituted of concrete with long fibers (rebars) bundles oriented in different directions embedded in it. The effects of the rebars are modeled by phenomenological constitutive models devised to reproduce the axial non-linear behavior, as well as the bond-slip and dowel action. The paper presents the constitutive models assumed for the components and the compatibility conditions chosen to constitute the composite. Numerical analyses of existing experimental reinforced concrete members are presented, illustrating the applicability of the proposed methodology.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.2397-2401
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• 2005

It is well understood that force reflecting coupled with visual display can be an important two-way communication channel in human-computer interaction. In this work, important components for a high-fidelity system bandwidth are force reflecting device and that all the computations including contact determination and response computation have to be performed in less than a millisecond. This paper describes a force-reflecting device and an embedded controller. The realized force-reflecting device is based on a novel serial type mechanical structure, and features compactness, high sustained output force capability, low friction, zero backlash, and enough workspace. The embedded controller reduces software computational load via main processor and simplifies hardware strictures by the time-division control. The device is integrated with existing dynamic simulation algorithms running separate workstation, so that objects can be manipulated in real time and the corresponding forces felt back by the operator.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.342-345
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• 2002

As the size of chip components and module decreases, new patteming method for fine line and geometry is needed. So far, in LTCC(Low Temperature Cofired Ceramic) process, screen printing method has been used generally. But screen printing method has some disadvantages as follows. First, the geometry including line, vias, etc. smaller than $100{\mu}m$ can't be evaluated easily. Second, the patterned dimension is different from designed value, which makes distortion in charactersitics of not only chip components but also modules. Thick film lithography has advantages of thick film screen printing process, low cost and thin film process, fine line feasibility. Using this method, the line with $30{\mu}m$ width and the geometry with expected dimension can be evaluated. In this study, the fine line with $35{\mu}m$ line/space is formed and the embedded capacitor with very small tolerance is developed using thick film lithography.

• ETRI Journal
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• v.40 no.6
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• pp.759-773
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• 2018

Uncore components such as on-chip memory systems and on-chip interconnects consume a large amount of energy in emerging embedded applications. Few studies have focused on next-generation analytical models for future chip-multiprocessors (CMPs) that simultaneously consider the impacts of the power consumption of core and uncore components. In this paper, we propose a convex-optimization approach to design heterogeneous uncore architectures for embedded CMPs. Our convex approach optimizes the number and placement of memory banks with different technologies on the memory layer. In parallel with hybrid memory architecting, optimizing the number and placement of through silicon vias as a viable solution in building three-dimensional (3D) CMPs is another important target of the proposed approach. Experimental results show that the proposed method outperforms 3D CMP designs with hybrid and traditional memory architectures in terms of both energy delay products (EDPs) and performance parameters. The proposed method improves the EDPs by an average of about 43% compared with SRAM design. In addition, it improves the throughput by about 7% compared with dynamic RAM (DRAM) design.