• Journal of the Korean Vacuum Society
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• v.3 no.1
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• pp.59-64
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• 1994

극소전자 디바이스의 고집적화와 더불어 박막배선의 선폭은 0.5$\mu$m이하까지 축소되며 초고집적 submicron 박막금속화가 진행되고 있다. 미세회로에 적용되어지는 배선재료는 인가되는 고전류밀도로 인하여 electromigration 에 의한 결함이 쉽게 발생한다는 단점이있다. 금속박막 전도체위의 dielectric overlayer는 electromigration 에 대한 passivation 효과를 보여 극소전자 디바이스의 평균수명을 향상시 킨다.본 연구에서는 박막금속화에서 dielectric overlayer의 passivation 효과를 알아보기 위하여 약 3000 $\AA$ 두께의 Al,Al-1%Si, Ag 그리고 Cu 박막배선위에 증착하여 SiO2절연보호막의 유무에 따른 박막배선 의 수명변화 및 신뢰도를 측정하였다. 박막배선에 인가된 전류밀도는 1x106 A/cm2와 1x107 A/cm2 이었다. SiO2 dielectric overlayer는 Al,Al-1%Si Ag. Cu 박막배선에서는 electromigration에 대한 보호막 혀과를 보이며 평균수명을 모두 향상시킨다. SiO2 passivation 효과는 Al, Ag, Cu 박막중 Cu 박막배선에서 가 장 크게 나타났다. SiO2 dielectric overlayer가 형성되지 않은 경우 Al 박막배선의 수명이 가장 긴 것으 로 나타났으나 SiO2 가 형성된 경우는 Cu 박막배선의 수명이 가장 길게 나타났다.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.14 no.2
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• pp.58-62
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• 2004

The shape evolution of the interface void of copper metallization for intergrated circuits under electromigration stress is modeled. A 2-dimensional finite-difference numerical method is employed for computing time evolution of the void shape driven by surface diffusion, and the electrostatic problem is solved by boundary element method. When the diffusion coefficient is isotropic, the numerical results agree well with the known case of wedge-shape void evolution. The numerical results for the anisotropic diffusion coefficient show that the initially circular void evolves to become a fatal slitlike shape when the electron wind force is large, while the shape becomes non-fatal and circular as the electron wind force decreases. The results indicate that the open circuit failure caused by slit-like void shape is far less probable to be observed for copper metallization under a normal electromigration stress condition.

• Proceedings of the KIEE Conference
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• 1995.11a
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• pp.364-366
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• 1995

We investigated the Electromigration characteristics in Cu alloyed Al line and the effect of Ti/TiN barrier layer on the characteristics. Test structures were fabricated by wafer level and 50% failure times were tested in the condition of j= 2 MA/$cm^3$, T= 300$^{\circ}C$. The reliability of Al line was improved which was 0.5%Cu Alloyed, but Ti/TiN under layer deteriorated the reliability while TiN over layer improved the characteristics.

• Journal of Korean Vacuum Science & Technology
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• v.7 no.2
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• pp.39-44
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• 2003

Recent ULSI and multilevel structure trends in microelectronic devices minimize the line width down to a quarter micron and below, which results in the high current densities in thin film interconnections. Under high current densities, an EM(electromigration) induced failure becomes one of the critical problems in a microelectronic device. This study is to improve thin film interconnection materials by investigating the EM characteristics in PSG(phosphosilicate glass)/SiO$_2$ passivated Al-l%Si thin film interconnections. Straight line patterns, wide and narrow link type patterns, and meander type patterns, etc. were fabricated by a standard photholithography process. The main results are as follows. The current crowding effects result in the decrease of the lifetime in thin film interconnections. The electric field effects accelerate the decrease of lifetime in the double-layered thin film interconnections. The lifetime of interconnections also depends upon the current conditions of P.D.C.(pulsed direct current) frequencies applied at the same duty factor.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.4
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• pp.17-24
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• 2008

Thermal annealing and electromigration test were performed at $150^{\circ}C$ and $150^{\circ}C,\;5{\times}10^4\;A/cm^2$ conditions, respectively, in order to compare the growth kinetics of intermetallic compound(IMC) in Cu pillar bump. The quantitative interfacial adhesion energy with annealing was measured by using four-point bending strength test in order to assess the effect of IMC growth on the mechanical reliability of Cu pillar bump. Only $Cu_6Sn_5$ was observed in the Cu pillar/Sn interface after reflow. However, $Cu_3Sn$ formed and grew at Cu pillar/$Cu_6Sn_5$ interface with increasing annealing and stressing time. The growth kinetics of total($Cu_6Sn_5+Cu_3Sn$) IMC changed when all Sn phases in Cu pillar bump were exhausted. The complete consumption time of Sn phase in electromigration condition was faster than that in annealing condition. The quantitative interfacial adhesion energy after 24h at $180^{\circ}C$ was $0.28J/m^2$ while it was $3.37J/m^2$ before annealing. Therefore, the growth of IMC seem to strongly affect the mechanical reliability of Cu pillar bump.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.193-215
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• 2003

Fracture Mechanism of Flip Chip Electromigration Failure - Mostly caused by Cathode Depletion at the UBM/Solder Interface Guideline to Increase Electromigration Resistance Material Selection: Sn/Ag(/Cu) > Pb/63Sn Cu UBM > Ni UBM (but, Solder Material combination) UBM Design: thick UBM is preferable (but, Stress Issue) Pad open/UBM size: as large as possible (but, pad size & pitch limit)

• Journal of the Korean Vacuum Society
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• v.11 no.4
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• pp.194-200
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• 2002

MOCVD(metal-organic chemical vapor deposition) copper thin film was annealed at various conditions and the eletrical properties and micro-structures were investigated to find the optimal annealing condition and its effect. Cu thin film annealed at Ar 1 torr, $400^{\circ}C$ had the most improved resistivity of 1.98 $\mu\Omega$cm, and texture; the ratio of $I_{(111)}/I_{(200)}$ was varied from 2.03 to 3.11, and Cu thin film annealed at Ar 1 torr, $450^{\circ}C$ had the largest grain size and uniformity. After the annealing, the EM(electromigration) test was followed to ensure the improved properties by annealing. Compare to other conditions, Cu patterns annealed at Ar 1 torr, $400 ^{\circ}C$ had the most improved properties when it came to the EM resistance, which was due to the low resistivity, the preferential evolution of texture to (111) plane, and the reduction of surface roughness of annealed copper film.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.1 s.34
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• pp.53-58
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• 2005

We researched damage formation and failure mechanism under DC(direct current) and AC(alternative current) in order to estimate reliability of Cu interconnects in ULSI. Higher current density and temperature induces more short TTF(time to failure) during interconnects carry DC. Measurement reveals that Cu electromigration has activation energy of 0.96eV and current density exponent value of 4. Thermal fatigue is occurred under DC, and higher frequency and ${\Delta}$T value gives more severe damage during interconnects carry AC Through failure morphology analysis with respect to texture, we observed that damages had grown widely and facetted grains had appeared in (100)grain but damages in (111) had grown thickness direction of line and had induced a failure rapidly.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.5
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• pp.215-221
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• 2014

In this paper, the improved power durability test system and method for an reliability analysis of SAW device is proposed and the failure mechanism through failure analysis is analyzed. As a result of the failure analysis using microscope, SEM and EDX, the failure mechanism of the SAW device is electromigration due to joule heating under high current density and high temperature condition. The electromigration makes voids and hillocks in the IDT electrode and the voids and hillocks can lead to short circuit and open circuit faults, respectively, increasing the insertion loss of an SAW filter. The accelerated life testing of the SAW filter for 450MHz CDMA application using the proposed power durability test system and method is carried out. $B_{10}$ lifetime of the SAW filter using Eyring model and Weibull distribution is estimated as about 98,500 hours.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.6
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• pp.436-441
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• 1999

Joule heating effect in EM(Electromigration) test were performed on a bend test structure. EM test is done under high current densities(1.0-2.5MA/cm2), which leads to joule heating. Since joule heating is added to the controlled oven(stress) temperature, themetal line temperature is higher than the stress temperature. The increase in the stress temperature due to joule heating is important because EM phenomena and metal line failure are related to the stress temperature. In this paper, metal line was stressed with a current density of 1.0 MA/$cm^2$, 1.5MA/$cm^2$, 2.0MA/$cm^2$, 2.5MA/$cm^2$, for 1200 sec and temperature increase due to joule heating was less than $10^{\circ}C$. Also it took 30 minutes for the metal line to equalized with oven temperature. Recommendations are given for the EM test to determine the initial resistance of EM test structure under stress temperature and current density.