• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.490.2-490.2
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• 2014

Since the general solar cells accept sun light at the front side, excluding the electrode area, electrons move from the emitter to the front electrode and start to collect at the grid edge. Thus the edge of gridline can be important for electrical properties of screen-printed silicon solar cells. In this study, the improvement of electrical properties in screen-printed crystalline silicon solar cells by contact treatment of grid edge was investigated. The samples with $60{\Omega}/{\square}$ and $70{\Omega}/{\square}$ emitter were prepared. After front side of samples was deposited by SiNx commercial Ag paste and Al paste were printed at front side and rear side respectively. Each sample was co-fired between $670^{\circ}C$ and $780^{\circ}C$ in the rapid thermal processing (RTP). After the firing process, the cells were dipped in 2.5% hydrofluoric acid (HF) at room temperature for various times under 60 seconds and then rinsed in deionized water. (This is called "contact treatment") After dipping in HF for a certain period, the samples from each firing condition were compared by measurement. Cell performances were measured by Suns-Voc, solar simulator, the transfer length method and a field emission scanning electron microscope. According to HF treatment, once the thin glass layer at the grid edge was etched, the current transport was changed from tunneling via Ag colloids in the glass layer to direct transport via Ag colloids between the Ag bulk and the emitter. Thus, the transfer length as well as the specific contact resistance decreased. For more details a model of the current path was proposed to explain the effect of HF treatment at the edge of the Ag grid. It is expected that HF treatment may help to improve the contact of high sheet-resistance emitter as well as the contact of a high specific contact resistance.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2011년도 추계학술발표대회
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• pp.30.1-30.1
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• 2011

Silicon is one of useful materials in various industry such as semiconductor, solar cell, and secondary battery. The metallic silicon produces generally melting process for ingot type or chemical vapor deposition (CVD) for thin film type. However, these methods have disadvantages of high cost, complicated process, and consumption of much energy. Electrodeposition has been known as a powerful synthesis method for obtaining metallic species by relatively simple operation with current and voltage control. Unfortunately, the electrodeposition of the silicon is impossible in aqueous electrolyte solution due to its low oxidation-reduction equilibrium potential. Ionic liquids are simply defined as ionic melts with a melting point below $100^{\circ}C$. Characteristics of the ionic liquids are high ionic conductivities, low vapour pressures, chemical stability, and wide electrochemical windows. The ionic liquids enable the electrochemically active elements, such as silicon, titanium, and aluminum, to be reduced to their metallic states without vigorous hydrogen gas evolution. In this study, the electrodeposion of silicon has been investigated in ionic liquid of 1-butyl-3-methylpyrolidinium bis (trifluoromethylsulfonyl) imide ([bmpy]$Tf_2N$) saturated with $SiCl_4$ at room temperature. Also, the effect of electrode materials on the electrodeposition and morphological characteristics of the silicon electrodeposited were analyzed The silicon electrodeposited on gold substrate was composed of the metallic Si with single crystalline size between 100~200nm. The silicon content by XPS analysis was detected in 31.3 wt% and the others were oxygen, gold, and carbon. The oxygen was detected much in edge area of th electrode due to $SiO_2$ from a partial oxidation of the metallic Si.

• 한국구조물진단유지관리공학회 논문집
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• 제23권6호
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• pp.113-119
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• 2019

본 연구는 전기비저항 측정시 실험체 크기에 따른 영향에 대해 비저항추정모델을 이용한 해석적 검토를 목적으로 한다. 실험에서는 콘크리트 실험체를 제작하여 전극 간격별 겉보기 비저항 측정하였다. 측정된 겉보기 비저항은 실험체 크기가 작아지고 외측(가장자리)에 가까울수록 겉보기 비저항치의 왜곡현상이 심해진다는 것을 확인할 수 있었다. 측정치와 해석치의 비교·분석 결과, 실험체 크기의 영향성 검토에 REM이 활용될 수 있을 것으로 기대된다.

• 한국전기전자재료학회논문지
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• 제13권9호
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• pp.729-734
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• 2000

Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• 대한전자공학회논문지SD
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• 제39권5호
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• pp.1-7
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• 2002

Deep sub-micron bulk CMOS circuits require gate electrode materials such as metal silicide and titanium silicide for gate oxides. Many authors have conducted research to improve the quality of the sub-micron gate oxide. However, few have reported on the electrical quality and reliability of an ultra-thin gate. In this paper, we will recommend a novel shallow trench isolation structure and a two-step TiS $i_2$ formation process to improve the corner metal oxide semiconductor field-effect transistor (MOSFET) for sub-0.1${\mu}{\textrm}{m}$ VLSI devices. Differently from using normal LOCOS technology, deep sub-micron CMOS devices using the novel shallow trench isolation (STI) technology have unique "inverse narrow-channel effects" when the channel width of the device is scaled down. The titanium silicide process has problems because fluorine contamination caused by the gate sidewall etching inhibits the silicide reaction and accelerates agglomeration. To resolve these Problems, we developed a novel two-step deposited silicide process. The key point of this process is the deposition and subsequent removal of titanium before the titanium silicide process. It was found by using focused ion beam transmission electron microscopy that the STI structure improved the narrow channel effect and reduced the junction leakage current and threshold voltage at the edge of the channel. In terms of transistor characteristics, we also obtained a low gate voltage variation and a low trap density, saturation current, some more to be large transconductance at the channel for sub-0.1${\mu}{\textrm}{m}$ VLSI devices.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.480-480
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• 2008

Vacuum circuit breaker(VCB) is now emerging as an alternative of gas circuit breaker(GCB) which uses SF6 gas as insulating material whose dielectric strength is outstanding. But we have to reduce SF6 gas because SF6 gas is one of greenhouse gas and efforts to reduce greenhouse gas are now trend of the world. Therefore, we can say VCB is the optimal alternative of GCB because vacuum is environmentally friendly. The vacuum interrupter is the core part of VCB to interrupt arcing current. There are mainly two methods to extinguish arc. One is radial magnetic field (RMF) method and the other is axial magnetic field (AMF) method. We deals with RMF method in this paper. Compared with AMP, RMF arc quenching method has different principle to extinguish arc. In case of RMF method, pinch effect is much larger than AMF method. Because of pinch effect RMF type contact electrodes have the single large spot which is severly damaged and melted while AMF type contact electrodes have small and multiple spots which are slightly damaged and melted. To prevent contact electrode being damaged and melted from high temperature-arc, RMF method uses Lorentz force to move arc. In this paper we calculated and compared the arc driving force of two cases and we analyzed the force acting on each part of arc by means of commercial finite element method software Maxwell 3D. They have 3petals and we considered two cases. One is the case when fixed(upper) and movable(lower) contacts are in mirror arrangement (Case 1). The other is the case when one of two contacts (movable contact) is revolved at maximum angle as possible as it can be (Case 2). And at each case above, we analyzed arc driving force at two positions, position 1 is the closest to the center of contact and position 2 is near the edge of petal on fixed contact. As a result we could find that Case 2 generated stronger arc driving force than Case 1 at position 1. But at position 2 Case 1 generated stronger arc driving force than Case 2. This simulation method can contribute to optimizing spiral-type electrode designs in a view of arc driving force.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.27-27
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• 2008

The different concentration Indium doped ZnO:Al films were grown on glass substrates (Corning 1737) at $200^{\circ}C$ by pulsed laser deposition. The indium doping in AZO films shows the critical effect on the crystallinity, resistivity, and optical properties of the films. The AZO films doped with 0.3 atom % indium content exhibit the highest crystallinity, the lowest resistivity of $4.5\times10^{-4}\Omega$-cm, and the maximum transmittance of 93%. The resistivity of the indium doped-AZO films is strongly related with the crystallinity of the films. The carrier concentration in the indium doped-AZO films linearly increases with increasing indium concentration. The mobility of the AZO films with increasing indium concentration was reduced with an increase in carrier concentration and the decrease in mobility was attributed to the ionized impurity scattering mechanism. In an optical transmittance, the shift of the optical absorption edge to shorter wavelength strongly depends on the electronic carrier concentration in the films.

• 마이크로전자및패키징학회지
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• 제7권3호
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• pp.45-54
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• 2000

Stamped Leadframe에 전해연마를 적용하여 가공면에 존재하는 버어(burr)의 제거와 그에따른 잔류응력 완화효과를 보았다. 또한 표면 청정화에 따른 은(Ag)도금면 및 리드프레임 표면 품질의 향상이 있었다. 인산 60% 전해연마액에 고정 전류값 5A와 극간거리 3.0 cm의 조건하에 Alloy42 원소재 리드프레임은 $70^{\circ}C$에서 120초간, C194 원소재 리드프레임은 $50^{\circ}C$에서 90초간 전해연마 하였다. XRD 반가폭(FWHM)을 이용한 잔류응력 측정결과 전해 연마 처리후의 잔류응력값이 스탬핑 이전상태로 회복되었으며, AFM를 이용하여 표면 거칠기 측정결과 Alloy42원소재 리드프레임은 0.079 $\mu\textrm{m}$, C-194원소재 리드프레임은 0.014 $\mu\textrm{m}$의 R$_{근}$값으로 거칠기의 향상이 있었다. XRF를 이용한 도금두께 측정 결과 0.4~0.5 $\mu\textrm{m}$ 정도 두께편차 균일성의 향상이 있었으며, wire bonding온도에서의 bake test결과 금선(gold wire) 과의 접합강도를 높일수 있는 적절한 크기로의 결정립 성장이 관찰되었다 3차원 자동측정 및 표면 경도 측정 통하여 전해연마로 인한 리드프레임 중요부위 치수변화의 신뢰성을 확인할수 있었다.다.