• Journal of Institute of Control, Robotics and Systems
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• v.5 no.6
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• pp.691-697
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• 1999

This paper describes the implementation of a high speed image processing board. This image processing board is consist of a image acquisition part and a image processing part. The image acquistion part is digitizing the image input data from CIS and save it to the dual port RAM. By putting on the dual port memory between two parts, during acquistion of image, the image processing part can be effectively processing of large-volume image data. Most of all image preprocessing part are integrated in a large-scaled FPGA. We arwe using ADSP-2181 of the Analog Device Inc., LTD. for a image processing part, and using the available all memory of DSP for the large-volume image data. Especially, using of IDMA exchanges the data with the external microprocessor or the external PC, and can watch the result of image processing and acquired image. Finally, we show that an implemented image processing board used for the simulation of image retreval by the one of the typical application.

• Journal of IKEEE
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• v.28 no.1
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• pp.26-32
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• 2024

Recently, various video resolution formats have emerged, and digital devices have built in dedicated scaler chips to support them by enlarging or reducing the resolution of input videos. Therefore, the performance and hardware size of scaler chips are important. In this paper, the combinatorial interpolation scaler algorithm proposed by Han is used to design the hardware using the line memory structure with dual-clock proposed by Han and Jung. The proposed hardware is capable of real-time processing in QHD environments, designed using Verilog, and validated using Xilinx's Vivado 2023.1. We also verify the performance of Han's proposed algorithm with a quantitative numerical evaluation of the proposed hardware.

• Korean Journal of Cognitive Science
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• v.18 no.2
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• pp.159-178
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• 2007

Lee & Kang (2002) showed that simultaneous phonological rehearsal significantly delayed the performance of multiplication but not subtraction, whereas holding an image in the memory delayed subtraction but not multiplication. This result indicated that arithmetic function is related to working memory in a subsystem-specific manner. The aim of the current study was to examine the neural correlates of previous finding using fMRI. For this goal, dual task conditions that required suppression or no suppression were manipulated. In general, several areas were more activated in the interference conditions than in the less interference conditions, although both conditions were dual condition. More important finding is that the specific areas activated in the phonological suppression rendition were right inferior frontal gyrus, left angular, and inferior parietal lobule, while the areas activated in the other condition were mainly in the right superior temporal gyrus and anterior cingulate gyrus. Furthermore, the areas activated in the phonological or visual less suppression condition were right medial frontal gyrus, left middle frontal gyrus, and bilateral medial frontal gyri, anterior cingulate cortices, and parahippocampal gyri, respectively. These results revealed that sharing the processing code invokes interference, and its neural basis.

• Journal of the Korean Society of Physical Medicine
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• v.17 no.1
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• pp.93-108
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• 2022

PURPOSE: This review sought to confirm the correlation between dual-task gait and cognitive function in cognitively impaired and healthy older adults. METHOD: We used four databases (DBs), Pubmed, Cochrane library, Kmbase, and Koreamed. Searches were carried out according to the PICOS method, P (participants) were the elderly (above 65 years) with cognitive decline, I (intervention) was walking with dual tasks, C (control group) comprised the elderly without cognitive decline, O (outcome) was the correlation between gait and cognitive function and S (study) was the cross-sectional study. For the methodological quality assessment of each study, we used the Quality Assessment Tool for Observation Cohort and Cross-Sectional Studies provided by the National Institutes of Health (NIH). RESULTS: A total of 10 articles were included in this systematic review. For the components of gait, we used pace, rhythm, and variability and we observed that mild cognitive impairment mostly causes low gait performance while performing dual tasks. Among the 10 articles, 9 articles studied pace, of which 7 showed significant results. However, 2 were not significant. Also, 1 article that studied rhythm and 3 articles that studied variability showed significant results. The methodological quality of the 10 studies was fair. CONCLUSION: Gait pace was found to have a high correlation between memory, which is a cognitive ability, and overall cognitive function. It was observed that older adults with mild cognitive impairment have reduced gait pace in single-task walking, and further decrease in dual-task gait pace shows the correlation between memory and gait pace during walking.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.8
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• pp.1548-1557
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• 1994

In this paper, the dual mode error correcting adaptive decoding algorithm which is adapted to the continuous phase frequency shift keying(CPFSK) modulation is presented as a technique for overcoming the distortion that reveals from the Rayleigh fading channel. The dual mode adaptive decoder nominally operates as a Viterbi decoder and switches to the burst error correcting mode, whenever the decoder detects an uncorrectable burst error pattern. Under the fading channel environment and when the usable memory quantity is restricted, the dual mode adaptive decoding algorithm shows an advantage in the BER performance over the interleaving technique, and also obtains the merit of not needing the large time delay that the interleaving technique requires. The experimental results from the computer simulation demonstrate the performance of the algorithm and verify the theoretical results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.6B
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• pp.1183-1190
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• 1999

This paper presents an efficient hardware architecture to improve the frame memory interface occupying the largest hardware area together with motion estimator in implementing MPEG-2 video encoder as an ASIC chip. In this architecture, the memory size for internal data buffering and hardware area for frame memory interface control logic are reduced through the efficient memory map organization of the external SDRAM having dual bank and memory access timing optimization between the video encoder and external SDRAM. In this design, 0.5 m, CMOS, TLM (Triple Layer Metal) standard cells are used as design libraries and VHDL simulator and logic synthesis tools are used for hardware design add verification. The hardware emulator modeled by C-language is exploited for various test vector generation and functional verification. The architecture of the improved frame memory interface occupies about 58% less hardware area than the existing architecture[2-3], and it results in the total hardware area reduction up to 24.3%. Thus, the (act that the frame memory interface influences on the whole area of the video encoder severely is presented as a result.

• Korean Journal of Cognitive Science
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• v.7 no.3
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• pp.115-134
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• 1996

The study was designed to investigate implicit and explicit memory for words with processing theory.From experiment 1 to experiment 3,in a study phase,subjects first viewed stimulus words and were required to rate likeness of words of semantic processing task and to count lines of words of perceptual processing task.In a test phase,subjects were tested by implicit word completion task and explicit cued recall task.In experiment 1,levels of processing (LOP)effects were examined.Lop effects were obtained on the explicit memory tasks but not on the implicit memory tasks.In experiment 2,repertition of perceptual processing task influenced onlu implicit memory task.In experiment 3,bepertiotion of semantic processing task affected both implicit memory task and explicit memory task.These findings suggest that repetition effect of stimulus words are explanied better in dual process theory than transfer-appropriate processing theory.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.3 s.357
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• pp.43-51
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• 2007

OneNAND flash combines the advantages of NAND and NOR flash, and has become an alternative to the former. But the advanced features of OneNAND flash are not utilized effectively in demand paging systems designed for NAND flash. We propose delayed dual buffering, a demand paging system which fully exploits the random-access I/O interface and dual page buffers of OneNAND flash demand paging system. It effectively reduces the time of page transfer from the OneNAND page buffer to the main memory. On average, it achieves and 28.5% reduction in execution time and 4.4% reduction in paging system energy consumption.

• Journal of the Korean institute of surface engineering
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• v.53 no.3
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• pp.124-129
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• 2020

This study is for the development of high temperature ALD SiO₂ film process, optimized for gap-fill process in manufacturing memory products, using a space-divided PE-ALD system equipped with an independent control dual plasma system and orbital moving unit. Space divided PE-ALD System has high productivity, and various applications can be applied according to Top Lid Design. But space divided ALD system has a limitation to realize concentric deposition map due to process influence due to disk rotation. In order to solve this problem, we developed an orbit rotation moving unit in which disk and wafer. Also we used Independent dual plasma system to enhance thin film properties. Improve productivity and film density for gap-fill process by having deposition and surface treatment in one cycle. Optimize deposition process for gap-fill patterns with different depths by utilizing our independently controlled dual plasma system to insert N₂and/or He plasma during surface treatment, Provide void-free gap-fill process for high aspect ratio gap-fill patterns (up to 50:1) with convex curvature by adjusting deposition and surface treatment recipe in a cycle.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.26 no.6
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• pp.1443-1454
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• 2016

Balanced encoding method that implement Dual-rail logic style based on hardware technique to software is efficient countermeasure against side-channel analysis without additional memory. Since balanced encoding keep Hamming weight and/or Hamming distance of intermediate values constantly, using this method can be effective as countermeasure against side channel analysis due to elimination of intermediate values having HW and/or HD relating to secret key. However, former studies were presented for Constant XOR operation, which can only be applied to crypto algorithm that can be constructed XOR operation, such as PRINCE. Therefore, our first proposal of new Constant ADD, Shift operations can be applied to various symmetric crypto algorithms based on ARX. Moreover, we did not used look-up table to obtain efficiency in memory usage. Also, we confirmed security of proposed Constant operations with Mutual Information Analysis.