• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.2
• /
• pp.1-13
• /
• 1999

As the complexity of DSP (Digital Signal Processing) applications increases, the need for new architectures supporting efficient high-level language compilers also grows. By combining several DSP processor specific features, such as single cycle MAC (Multiply-and-ACcumulate), direct memory access, automatic address generation, and hardware looping, with a RISC core having many general purpose registers and orthogonal instructions, a high-performance and compiler-friendly RISC-based DSP processors can be designed. In this study, we develop a code-converter that can exploit these DSP architectural features by post-processing compiler-generated assembly code, and evaluate the performance effects of each feature using seven DSP-kernel benchmarks and a QCELP vocoder program. Finally, we also compare the performances with several existing DSP processors, such as TMS320C3x, TMS320C54x, and TMS320C5x.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 1999.11a
• /
• pp.199-203
• /
• 1999

This paper is on the DSP system design and implementation for real time MPEG-2 AAC multichannel audio, and MPEG-4 object oriented audio coding. This DSP system employs two DSPs of the state of the art TMS320C6701, developed by TI semiconductor. DSP board has PCI interface for downloading application program and control the system. DSP board was designed to use for both encoder and decoder, by setting several switches. The system contains external input and output box also, for A/D and D/A conversion for eight channel audio. The input box converts multi channel digital audio to ADI format, that provides serial interface for eight channel digital audio. And the output box converts ADI format signal to multi channel audio. Through this ADI interface, DSP boards can be connected to input, output box. Implemented DSP system was tested for integration with MPEG-2 AAC encoder and decoder S/W. Currently the DSP system performs realtime AAC 4-channel audio encoding with two DSPs, and 8-channel decoding with one DSP.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.2
• /
• pp.72-81
• /
• 2002

A new high-performance DSP architecture is proposed, which behaves as a coprocessor of a 32bit microcontroller. Because the proposed DSP architecture is a dual MAC(Multiply and Accumulate) DSP architecture, it can process efficiently a number of SOP(sum of product) operations used in many DSP applications. In order to efficiently perform other operations such as pure additions without any restriction, a MAC is composed of a multiplier and a ALU placed in parallel. In addition, it is a 3-way superscalar architecture, which can issue 3 instructions at a time. The benchmark results with 3 thor dual MAC DSPs show that the proposed DSP has the best performance. Futhermore, it is proven that the proposed DSP is more efficient in memory usage, although the performance is comparable in some algorithms such as Viterbi decoding and FFT butterfly.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.23 no.6
• /
• pp.1409-1418
• /
• 1998

The recent audio CODEC(Coding/Decoding) algorithms are complex of several coding techniques, and can be divided into DSP tasks, controller tasks and mixed tasks. The traditional DSP processor has been designed for fast processing of DSP tasks only, but not for controller and mixed tasks. This paper presents a new architecture that achieves high throughput on both controller and mixed tasks of such algorithms while maintaining high performance for DSP tasks. The proposed processor, YSP-3, operates four algorithms while maintaining high performance for DSP tasks. The proposed processor, YSP-3, operates functional units (Multiplier, two ALUs, Load/Store Unit) in parallel via 4-issue super-scalar instruction structure. The performance evaluation of YSP-3 has been done through the implementation of the several DSP algorithms and the part of the AC-3 decoding algorithms.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.16 no.5
• /
• pp.1095-1101
• /
• 2012

This paper presents a design of a BLDC servo motor control system for the auto process of assembly and supply using DSP(Digital Signal Processor) controller and IGBT driver. The assembly and supply auto processing system needs torque, speed, position control of servo motor for variable action. This paper implements those servo control with vector control and space vector PWM(Pulse Width Modulation) technique. As CPU of controller, TMS320F240 DSP was adopted because it has PWM waveform generator, A/D converter, SPI(Serial Peripheral Interface) port and many input/output port etc. This control system consists of 3-level hierarchy structure that main host PC manages three sub DSP system which transfer downward command and are monitoring the states of end servo controllers. Each sub DSP system operates eight BLDC servo controllers which control BLDC motor using DSP and IPM. Between host system and sub DSP communicate with RS-422, between main processor and controller communicate with SPI port.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.11 no.8
• /
• pp.1478-1485
• /
• 2007

In this paper, a meteorological system including a wind speed & direction module and the DSP(Digital Signal Processor) sensor interface circuit board are proposed. This DSP system accepts and process the informations from a wind speed & direction module, the atmospheric pressure sensor, the ambient air temperature sensor and transfers it to the PC monitoring system. Especially, a wind speed & direction module and a DSP hardware are directly designed and applied. A wind speed & direction module have a construction that it have four film type RID(Resistive Temperature Detectors) resistive sensor adhered around the circular metal body heated constantly by heating coil for obtaining vector informations about wind. By this structure, the module is enabled precise measurement having a robustness about vibration, humidity, corrosion. A sensor signal processing circuit is using TMS320F2812 TI(Texas Instrument) Corporation high speed DSP. An economical meteorological system could be constructed through the data from wind speed & direction module and by the fast processing of DSP interface circuit board.

• Proceedings of the Korea Institute of Convergence Signal Processing
• /
• 2001.06a
• /
• pp.89-92
• /
• 2001

In this paper, as a study of programmable software radio digital communication, we implemented ASK(Amplitude Shift Keying), FSK(Frequency Shift Keying), and PSK(Phase Shift Keying) modulation using programmable software(algorithm) of DSP(Digital Signal Processor). Moreover, it is possible to select one of those three modulation methods by realizing on single DSP. We adopted Motorola DSP56002 and Crystal CS4215(A/D and D/A converter) for our purpose. The DSP56002 is 24-bit and operates 20 MIPS at 40 MHz, and the CS4215 is 16-bit and supports the maximum 50 kHz sampling frequency.

• Proceedings of the IEEK Conference
• /
• 2000.11b
• /
• pp.67-70
• /
• 2000

DSP is used for processing the digital data in such as the multimedia applications. Because the digital data of high rate is demanded more and more, high performance is increasingly required in DSP. In this paper, we discuss important issues for development of high performance DSP, analyze architectures of several commercial DSP chips, and propose a new architecture. Finally, we show that the new architecture has the highest performance.

• Proceedings of the Acoustical Society of Korea Conference
• /
• 1995.06a
• /
• pp.137-140
• /
• 1995

In the paper, CDMA's vocoder algorithm, QCELP, was analyzed. And, 16-bit programmable DSP core for QCELP was designed. When it is used two MACs in DSP, we can implement low-power DSP and estimate decrease of parameter computation speed. Also, we implemented in FIFO memory using register file to increase the access time of the data. This DSP was designed using logic synthesis tool, COMPASS, by top-down design methodology. Therefore, it is possible to cope with rapid change at mobile communication market.

• Proceedings of the IEEK Conference
• /
• 2003.07e
• /
• pp.1956-1959
• /
• 2003

본 논문에서는 HDTV(High Definition TV) 방송수신을 위한 DSP(Digital Signal Processor)기반의 HD급 비디오/오디오 디코더 시스템을 개발하고 그 성능을 확인하였다. DSP 플랫폼은 TI(Texas Instrument)사의 TMS320C6415를 대상으로 하였으며 TI의 DSP RTOS인 DSP/ BIOS를 이용하여 방송스트림인 TS(Transport Stream)을 분리하기 위한 TS Demuxer, MPEG-2 비디오 디코더 및 AC-3 오디오디코더 알고리즘을 통합하였으며, 각각의 알고리즘은 대상 DSP플랫폼인 TMS320C64x에 맞게 고정소수점 구조화 및 최적화를 실시하였다. 테스트를 위한 시스템은 스트리밍을 위한 호스트 PC와 PCI(Peripheral Component Interconnect)버스를 통해 연결된 DSP보드로 구성하였으며 실제 HDTV당송용 스트림과 SD(Standard Definition)급 스트림을 이용하여 성능을 확인하였다.