• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.2
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• pp.85-91
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• 2002

A novel multi-section power divider configuration is Proposed to obtain wide-band frequency performance up to microwave frequency region. Design procedures for the proposed microwave broadband power divider are composed of a Planar multi-section three-Ports hybrid and a waveguide transformer design procedures. The multi∼section power divider is based on design theory of the optimum quarter- wave transformer Furthermore, in order to obtain the broadband isolation performance between the two adjacent output ports, the odd mode equivalent circuit should be matched by using the lossy element such as resistor. The derived design formula for calculating these odd mode∼matching elements is based on the singly terminated filter design theory. The waveguide transformer section is designed to suppress the propagation of the higher order modes such as waveguide modes due to employing the metallic electric wall. Simulation and experiment show excellent performance of multi section power divider.

• Journal of Advanced Marine Engineering and Technology
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• v.33 no.1
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• pp.144-152
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• 2009

This paper propose highly miniaturized active $90^{\circ}C$ phase difference power divider and combiner for application to wireless communication system. The conventional passive $90^{\circ}C$ power divider and combiner cannot be integrated on MMIC because of their very large circuit size. Therefore, the highly miniaturized active $90^{\circ}C$ phase difference power divider and combiner are required for a development of highly integrated MMIC. In this paper, the highly miniaturized active $90^{\circ}C$ phase difference power divider and combiner employing InGaAs/GaAs HBT were designed, fabricated on GaAs substrate. According to the results, the circuit size of fabricated active $90^{\circ}C$ phase difference power divider and combiner were $1.67{\times}0.87$ mm and $2.42{\times}1.05$ mm, respectively, which were 31.6% and 2.2% of the size of conventional passive branch-line coupler. The output gain division characteristic of proposed divider circuit showed 8.4 dB and 7.9 dB respectively, and output phase difference characteristic showed $-89.3^{\circ}C$. The output gain coupling characteristic of proposed combiner circuit showed 9.4 dB and 10.5 dB respectively, and output phase difference characteristic showed $-92.6^{\circ}C$. The highly miniaturized active $90^{\circ}C$ phase difference power divider and combiner exhibited good RF performances compared with the conventional passive branch-line coupler.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.107-113
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• 2014

A VCO (Voltage Controlled Oscillator) and a divide-by-4 high speed frequency divider are implemented using 65nm CMOS technology for 60GHz wireless communication system. The mm-wave VCO was designed by NMOS cross-coupled LC type using current source. The architecture of the divide-by-4 high speed frequency divider is differential ILFD (Injection Locking Frequency Divider) with varactor to control frequency range. The frequency divider also uses current sources to get good phase noise characteristics. The measured results show that the VCO has 64.36~67.68GHz tuning range and the frequency divider divides the VCO output by 4 exactly. The high output power of 5.47~5.97dBm from the frequency divider is measured. The phase noise of the VCO including the frequency divider are -77.17dBc/Hz at 1MHz and -110.83dBc/Hz at 10MHz offset frequency. The power consumption including VCO is 38.4mW with 1.2V supply voltage.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.2
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• pp.245-251
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• 2017

The proposed variable pawer divider in this paper is composed of one equal power 2-way Wilkinson power divider, two variable phase shifters with 90-degree phase variation to be connected two output paths of the 2-way power divider, and one branchline coupler to combine output signals of two variable phase shifter. The proposed variable power divider can theoretically have an arbitrary power division ratio ranging from ${\infty}:1$ to ${\infty}:1$ due to 90-degrees phase variation of two phase shifter. The proposed power divider circuit fabricates on laminated TLX-9(h=20 mil, er=2.5; Taconic) with a center frequency of 1.7 GHz. The power division ratio of the fabricated prototype varies from about 1:100 to 200:1, with an input reflection characteristic(S11) of below -16 dB, an insertion loss of about -1.0 dB, and an isolation characteristic of below -17 dB between two output ports in the range 1.65-1.75 GHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.10 s.113
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• pp.953-958
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• 2006

A compact Wilkinson power divider with meta-material transmission line(MM-TL) is proposed. The divider is designed by adding the MM-TL with $+90^{\circ}$ phases shifting instead of the ${\lambda}_g/4$ with $-90^{\circ}$ phases shifting at a simple Wilkinson power divider. The MM-TL consists of three phase shifter unit cells and each cell has the characteristics of the $30^{\circ}$ phases shilling and 6 mm length. Therefore, the length of ${\lambda}_g/4(210 mm)$ TL with $-90^{\circ}$ phases shifting at a simple Wilkinson power divider can be reduced to 18 mm and the Wilkinson divider is very compact.

• Transactions on Electrical and Electronic Materials
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• v.15 no.6
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• pp.309-314
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• 2014

This work proposes an integrated high frequency divider with an inductive peaking technique implemented in a current mode logic (CML) frequency divider. The proposed divider is composed with a master-slave flip-flop, and the master-slave flip-flop acts as a latch and read circuits which have the differential pair and cross-coupled n-MOSFETs. The cascode bias is applied in an inductive peaking circuit as a current source and the cascode bias is used for its high current driving capability and stable frequency response. The proposed divider is designed with $0.18-{\mu}m$ CMOS process, and the simulation used to evaluate the divider is performed with phase-locked loop (PLL) circuit as a feedback circuit. A divide-by-two operation is properly performed at a high frequency of 20 GHz. In the output frequency spectrum of the PLL, a peak frequency of 2 GHz is obtained witha divide-by-eight circuit at an input frequency of 250 MHz. The reference spur is obtained at -64 dBc and the power consumption is 13 mW.

• Journal of Advanced Navigation Technology
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• v.17 no.1
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• pp.33-38
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• 2013

In this paper, we present the design and measured performances of an dual-band Gysel power divider based on band-stop characteristic. After the Gysel divider is designed by lumped elements at single operating frequency, and then using filter conversion technique the lumped elements were changed a band-stop characteristic with dual-band characteristics. The features of this design method are that ${\lambda}/4$ transmission line by replacing lumped elements suppressed harmonic characteristics and also can reduce the size. To validate of the proposed power divider, the divider has been designed and measured at 880 MHz and 1650 MHz dual frequencies. The measured performances of the Gysel divider agree with prediction results at two frequencies.

• Journal of Advanced Marine Engineering and Technology
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• v.37 no.1
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• pp.105-113
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• 2013

In this work, using a ${\pi}$-type multiple coupled microstrip line structure (MCMLS) and RCR (Resistor Capacitor Resistor) structure, we fabricated ultra-compact and high isolation Wilkinson power divider on GaAs MMIC (Monolithic Microwave Integrated Circuit). The line length of the Wilkinson power divider was reduced to about ${\lambda}$/46, and its size was 0.304 [$mm^2$], which is 12.1 % of conventional one. Compared with conventional Wilkinson power divider, isolation characteristic of the proposed Wilkinson power divider was highly improved by using RCR insertion method. The proposed Wilkinson power divider showed good RF performances in C/X band.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.5
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• pp.1134-1138
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• 2008

In this paper, the synthesis of distributed impedance transformers is presented that is essential for power divider design, whereby a broadband power divider is designed. Transfer functions of distributed transformers are synthesized with Chebyshev approximation, and their element values are calculated for various minimum insertion losses(MIL) and ripples. Desired performance of transformers is obtained by optimizing MIL's and ripples of a transfer function. As an application example, a four-way power divider is designed that operates over 2 to 8GHz frequency range. Experimental results are shown to approach the design performance, so transformer design by distributed network synthesis proves to be useful to power divider design.

• Journal of Advanced Navigation Technology
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• v.20 no.1
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• pp.59-64
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• 2016

This paper presents a high dividing ratio unequal dualband divider using coplanar waveguide (CPW) and shunt connected open stub transmission lines. In order to implement transmission lines for a dualband divider using design equations, the low impedance lines of divider can be realized a shunt connected open stub transmission line. Also, the high impedance lines are realized by CPW transmission lines. To certify the validity of an unequal dualband divider using CPW and shunt connected open stub transmission lines, the 10:1 unequal dualband divider is implemented at operating frequency of 1 and 2 GHz. Good experimental performance at each frequency are obtained, which are in good agreement with the simulated results.