• Proceedings of the Korean Society of Precision Engineering Conference
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• 2001.04a
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• pp.167-169
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• 2001

In this paper, a controller design for high speed and stiffness linear motor is implemented. The designed controller is mainly composed of speed and current controller, which are carried out by the high-speed digital signal processor(DSP). In addition the PWM inverter is controlled by space voltage PWM method. This system is implemented by using 32-bit DSP(TMS320C31), a high-integrated logic device(EPM7128), and IPM(Intelligent Power Module) for compact and powerful system design. The experimental results show the effective performance of controller for high speed and stiffness linear motor.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.257-260
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• 1999

We have designed a 32-bit RISC microprocessor with 16/32-bit fixed-point DSP functionality. This processor, called YRD-5, combines both general-purpose microprocessor and digital signal processor (DSP) functionality using the reduced instruction set computer (RISC) design principles. It has functional units for arithmetic operation, digital signal processing (DSP) and memory access. They operate in parallel in order to remove stall cycles after DSP and load/store instructions with one or more issue latency cycles. High performance was achieved with these parallel functional units while adopting a sophisticated 5-stage pipeline structure and an improved DSP unit.

• The Journal of the Acoustical Society of Korea
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• v.35 no.4
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• pp.272-279
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• 2016

In this paper, the realization of a hearing aid adaptively cancelling feedback noise was considered. Conventional least mean square method in time domain was transformed into frequency domain in order to minimize computational burden. The adaptive filter algorithm was evaluated by Matlab (Matrix laboratory), and it was confirmed by CSR 8675 Bluetooth DSP IC (Digital Signal Processor Integrated Circuit) chip firmware realization. Some remote control features by a smart phone was added to the smart hearing aid for user interface easiness.

• KIEE International Transactions on Power Engineering
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• v.4A no.3
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• pp.152-158
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• 2004

The passive filter is economic and efficient in suppressing harmonics but it may cause resonance problems and its performance is constantly dependent on power system impedance or working conditions of loads. This paper presents the DSP (Digital Signal Processor)-based control system, which automatically controls the passive filter in order to solve these problems. The control system can automatically control the passive filter according to working conditions of loads and measured harmonics, reactive power, power factor and so on. Experimental results in the power system using the 100HP DC motor drive are presented in order to verify the performance of the control system.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.50 no.6
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• pp.266-271
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• 2001

In this paper, a controller design for coreless linear synchronous motor is proposed. The designed controller is mainly composed of speed and current control, which are carried out by the high-speed digital signal processor(DSP). In addition the PWM inverter is controlled by space voltage PWM method. This system is implemented using by 32-bit DSP(TMS320C31), a high-integrated logic device(EPM940), and IPM(Intelligent Power Modules) for compact and powerful system design. The experimental results show the effective performance of controller for coreless linear synchronous motor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10C
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• pp.999-1007
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• 2002

In this paper, the operation of matched filter for searching initial synchronization in direct sequence spread spectrum receiver is studied. The implementation model of the matched filter by HDL (Hardware Description Language) is proposed. The model has an architecture based on parallelism and pipeline for fast processing, which includes circular buffer, multiplier, adder, and code look-up table. The performance of the model is analyzed and compared with the implementation by a conventional digital signal processor. It is implemented on a FPGA (Field Programmable Gate Array) and its operation is validated in a timing simulation result.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.7
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• pp.1102-1109
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• 2001

This paper presents the new architecture of an adaptive predistortion linearizer using the polynomial type predistorter. In the proposed linearizer, most of the processes, including the predistortion, are performed with a digital signal processor(DSP). The recursive least squares(RLS) algorithm is employed for the optimization process to minimize the errors between the predistorter and postdistorter output signals. Simulation results demonstrate that the adjacent channel power ratio(ACPR) is improved by greater than 40 dB at the band edge with linearization. The convergence and reconvergence performance of the linearizer is also satisfactory.

• Journal of Electrical Engineering and Technology
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• v.3 no.2
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• pp.243-253
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• 2008

This paper deals with the analysis, design, and implementation of a single phase AC-DC Zeta converter with high frequency transformer isolation and power factor correction(PFC) in two modes of operation, discontinuous current mode of operation(DCM), and continuous current mode of operation(CCM). A Digital Signal Processor(DSP) based implementation is carried out for validation of the Zeta converter developed design in discontinuous mode of operation. A comparison of both modes of operation is presented for a 1kW power rating from the point of view of steady state and dynamic behavior, power quality, simplicity, control technique, device rating, and converter size. The experimental results of a developed prototype of Zeta converter are presented for validation of the developed design. It is observed that CCM is most suitable for higher power applications where it requires some complex control and sensing of the additional variables.

• Proceedings of the KIEE Conference
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• 2003.07d
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• pp.2438-2440
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• 2003

This thesis presents a design methodology of a Digital Servo Signal Processor for high speed CD-ROM drive systems. The proposed Digital Servo Signal Processor enables us to develop CD-related systems for the very high speed applications and is one of the key components of the CD-ROM systems. The proposed center compensation servo control is newly built for a actuator shaking due to the fast response of a step motor when it jumps to a long distance. From experimental results, we can see that the performance of the control system is improved greatly. The proposed servo algorithm shows a shorter setting time including a pull-in time and a faster access time.

• Journal of Advanced Marine Engineering and Technology
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• v.29 no.3
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• pp.251-259
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• 2005

A discrete time model reference adaptive control has been applied in order to compensate the nonlinear friction characteristics in a hydraulic proportional position control system. As nonlinear friction, static and coulomb friction forces are considered and modeled as dead zone and external disturbance respectively. The model reference adaptive control system consists of a cascade combination of the dead zone. external disturbance and linear dynamic block. For adaptive control experiment. the DSP(Digital Signal Processor) board has been interfaced the hydraulic proportional position control system. The experimental results show that the MRAC(Model Reference Adaptive Control) for compensation of static and coulomb friction are very effective.