• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.5
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• pp.609-615
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• 2020

In the modern society, the use of digital equipment is increasing along with the 4th industrial revolution, and the importance of image and signal processing is increasing. At the same time, research on noise reduction is being actively conducted. In this paper, we propose a switching filter algorithm for random-valued impulse noise cancellation. The proposed algorithm obtains the threshold value by determining the noise level present in the image, and threshold value is compared with the difference between the input pixel value and the reference value, and is used in the weight switching process of the filter. The final output of the filter is estimated by applying a pixel weight and a modified weight median filter according to the switching, and obtains a final output by comparing the estimated value with the input pixel value. To evaluate the performance of the proposed algorithm, we compared it with the existing methods using simulation and PSNR.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.6
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• pp.121-130
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• 2007

In this paper, we propose a reversible watermarking scheme in the JPEG compression domain. The reversible watermarking is useful to authenticate the content without the quality loss because it preserves the original content when embed the watermark information. In the internet, for the purpose to save the storage space and improve the efficiency of communication, digital image is usually compressed by JPEG or GIF. Therefore, it is necessary to develop a reversible watermarking in the JPEG compression domain. When the watermark is embedded, the lossless compression was used and the original image is recovered during the watermark extracting process. The test results show that PSNRs are distributed from 38dB to 42dB and the payload is from 2.5Kbits to 3.4Kbits where the QF is 75. Where the QF of the Lena image is varied from 10 to 99, the PSNR is directly proportional to the QF and the payload is around $1.6{\sim}2.8Kbits$.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.1
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• pp.33-39
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• 2007

Finite field multipliers are the basic building blocks in many applications such as error-control coding, cryptography and digital signal processing. Hence, the design of efficient dedicated finite field multiplier architectures can lead to dramatic improvement on the overall system performance. In this paper, a new bit serial structure for a multiplier with low latency in Galois field is presented. To speed up multiplication processing, we divide the product polynomial into several parts and then process them in parallel. The proposed multiplier operates standard basis of $GF(2^m)$ and is faster than bit serial ones but with lower area complexity than bit parallel ones. The most significant feature of the proposed architecture is that a trade-off between hardware complexity and delay time can be achieved.

• International Journal of Computer Science & Network Security
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• v.21 no.1
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• pp.143-151
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• 2021

The enormous prevalence of transferring official confidential digital documents via the Internet shows the urgent need to deliver confidential messages to the recipient without letting any unauthorized person to know contents of the secret messages or detect there existence . Several Steganography techniques such as the least significant Bit (LSB), Secure Cover Selection (SCS), Discrete Cosine Transform (DCT) and Palette Based (PB) were applied to prevent any intruder from analyzing and getting the secret transferred message. The utilized steganography methods should defiance the challenges of Steganalysis techniques in term of analysis and detection. This paper presents a novel and robust framework for color image steganography that combines Linear Congruential Generator (LCG), simulated annealing (SA), Cesar cryptography and LSB substitution method in one system in order to reduce the objection of Steganalysis and deliver data securely to their destination. SA with the support of LCG finds out the optimal minimum sniffing path inside a cover color image (RGB) then the confidential message will be encrypt and embedded within the RGB image path as a host medium by using Cesar and LSB procedures. Embedding and extraction processes of secret message require a common knowledge between sender and receiver; that knowledge are represented by SA initialization parameters, LCG seed, Cesar key agreement and secret message length. Steganalysis intruder will not understand or detect the secret message inside the host image without the correct knowledge about the manipulation process. The constructed system satisfies the main requirements of image steganography in term of robustness against confidential message extraction, high quality visual appearance, little mean square error (MSE) and high peak signal noise ratio (PSNR).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.10
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• pp.1483-1489
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• 2022

Recently, due to the influence of the 4th industrial revolution and the development of communication media, various digital video equipment are being used in industrial fields. Image data is easily damaged by noise in the process of acquiring and transmitting and receiving from the camera and sensor, and since the damaged image has a great effect on the processing of the system, noise removal is essential. In this paper, a weight filter algorithm using a weight graph is proposed to restoration images damaged by high-density impulse noise. The proposed algorithm obtains a weight graph using pixel values inside the filtering mask of the image, and restores the image by applying the final weight to the filtering mask. Simulation was conducted to analyze the noise removal performance of the proposed algorithm, and the magnified image and PSNR were used to compare with the existing method. The resulting image of the proposed algorithm showed excellent performance by removing high-density impulse noise.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.27 no.1
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• pp.54-61
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• 2023

With the development of IoT technologies and artificial intelligent, diverse digital image equipments are being used in industrial sites. Because image data can be easily damaged by noise while it's obtained with a camera or a sensor and the damaged image has a bad effect on the process of image processing, noise removal is being demanded as preprocessing. In this thesis, for the restoration of image damaged by the noise of random impulse, a switching filter algorithm based on noise estimation was suggested. With the proposed algorithm, noise estimation and error distraction were carried out according to the similarity of the pixel values in the local mask of the image, and a filter was chosen and switched depending on the ratio of noise existing in the local mask. Simulations were conducted to analyze the noise removal performance of the proposed algorithm, and as a result of magnified image and PSNR comparison, it showed superior performance compared to the existing method.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.39-46
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• 2016

This paper describes the third order feedforward delta-sigma modulator with inverter-based integrators and a 1.5bit comparator for the application of audio signal processing. The proposed 3rd-order delta-sigma modulator is multi-bit structure using 1.5 bit comparator instead of operational amplifier. This delta-sigma modulator has high SNR compared with single-bit 4th-order delta-sigma modulator in a low OSR. And it minimizes power consumes and simplified circuit structure using inverter-based integrator and using inverter-based integrator as analogue adder. The modulator was designed with 0.18um CMOS standard process and total chip area is $0.36mm^2$. The measured power cosumption is 28.8uW in a 0.8V analog supply and 66.6uW in a 1.8V digital supply. The measurement result shows that the peak SNDR of 80.7 dB, the ENOB of 13.1bit and the dynamic range of 86.1 dB with an input signal frequency of 2.5kHz, a sampling frequency of 2.56MHz and an oversampling rate of 64. The FOM (Walden) from the measurement result is 269 fJ/step, FOM (Schreier) was calculated as 169.3 dB.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.4
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• pp.68-74
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• 2017

This paper presents a joint demosaicking and arbitrary-ratio down sampling algorithm for color filter array (CFA) images. Color demosaiking is a necessary part of image signal processing pipeline for many types of digital image recording system using single sensor. Also, such as smart phone, obtained high resolution image from image sensor has to be down-sampled to be displayed on the screen. The conventional solution is "Demosaicking first and down sampling later". However, this scheme requires a significant amount of memory and computational cost. Also, artifacts can be introduced or details get damaged during demosaicking and down sampling process. In this paper, we propose a method in which demosaicking and down sampling are working simultaneously. We use inverse mapping of Bayer CFA and then joint demosaicking and down sampling with arbitrary-ratio scheme based on signal decomposition of high and low frequency component in input data. Experimental results show that our proposed algorithm has better image quality performance and much less computational cost than those of conventional solution.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2004.04a
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• pp.269-274
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• 2004

The marine electronic system for safe navigation such as ECDIS has been contributing to increase the safety of navigation, decreasing the mariner's load of navigation. The ECDIS should be developed and approved by international standard of IMO for performance standard and IEC for type-approval method and required results. However, these standards have some ambiguities for us not to directly adopt them for real approval system, so we should analyze them for more clear meaning and prepare our own detail standard for type-approval system. The first thing to do for the goal of this research was to analyze the standard in detail and make ambiguity be cleared in our own standards, considering each test item in view of test methodology. For the result of analysis we could develop more evident and detail type-approval standard for each test item with test technology needed. Especially, we developed the colour differentiation test process of ECDIS monitor, which include the colour differentiation formula derived from CIE colour scheme. Several test items require sensor informations of navigation equipment compatible with IEC 61162. We also developed the signal simulator for general messages of IEC 61162 that must be provided. Additionally, the type-approval processes and standards for Back-up arrangement and RCDS mode were developed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.447-458
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• 2003

A high speed multiplier is essential basic building block for digital signal processors today. Typically iterative algorithms in Signal processing applications are realized which need a large number of multiply, add and accumulate operations. This paper describes a macro block of a parallel structured multiplier which has adopted a 32$\times$32-b regularly structured tree (RST). To improve the speed of the tree part, modified partial product generation method has been devised at architecture level. This reduces the 4 levels of compression stage to 3 levels, and propagation delay in Wallace tree structure by utilizing 4-2 compressor as well. Furthermore, this enables tree part to be combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, multiplier architecture can be regularly laid out with same modules composed of Booth selectors, compressors and Modified Partial Product Generators (MPPG). At the circuit level new Booth selector with less transistors and encoder are proposed. The reduction in the number of transistors in Booth selector has a greater impact on the total transistor count. The transistor count of designed selector is 9 using PTL(Pass Transistor Logic). This reduces the transistor count by 50% as compared with that of the conventional one. The designed multiplier in 0.25${\mu}{\textrm}{m}$ technology, 2.5V, 1-poly and 5-metal CMOS process is simulated by Hspice and Epic. Delay is 4.2㎱ and average power consumes 1.81㎽/MHz. This result is far better than conventional multiplier with equal or better than the best one published.