• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.110-113
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• 1998

An analysis of the relationship between a linear amplifier chain and an analog-to-digital converter(ADC) in a digital microwave widevand receiver, with respect to sensitivity and dynamic range issues, is presented. The effects of gain, third-order intermodulation products and ADC characteristics on the performance of the receiver are illustrated and design criteria for the linear amplifier chain given a specified ADC are developed. A computer program is used to calculate theretical receiver performance based on gain and third-order intermodulation product selections. Simulated results are also presented and compared with theoretical values.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(4)
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• pp.259-262
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• 2002

In this paper, we present a hard disk drive embedded digital satellite receiver with scene change detection for video indexing. This receiver can store, retrieve and classify the broadcast data by implementing an interface between the conventional digital satellite receiver and digital storage media. Using this system, user can obtain more information for efficient video retrieval.

• 대한전기학회논문지
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• 제35권2호
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• pp.47-54
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• 1986

Hardware implementation of a 32-channel MFC digital receiver has not been easy and simple, because it requires real time processing of PCM data. In this paper, we introduce a method of designing an MFC digital receiver compactly by the channel distribution method. We have implemented the MFC digital receiver to process many cnannels by distributing channels of the TDM input data directly to the commercial digital signal processor chips(NEC uPD7720), and by carrying out the modified Goertzel Algorithm. The design of low cost, reliable, high speed, and compact MFC receiver will be shown.

• 한국컴퓨터정보학회논문지
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• 제24권7호
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• pp.71-78
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• 2019

This paper describes a design for a RF receiver to receive satellite digital audio service. The RF receiver designed in this study is a planar structure that is easy to install on the rooftop of a car and is compact in size. In addition, it can be applied to certain commercial models because it has low noise and high gain characteristics. The impedance bandwidth of antenna is 17.8%(415MHz), and the axial ratio is below 3dB as good properties for the bandwidth of 40MHz which is a satellite digital audio service band. Also, it had a broad radiation beamwidth of $95.41^{\circ}$ in H-plane and $117.45^{\circ}$ in E-plane. From the results of the field test of satellite digital audio service reception for the RF receiver, it demonstrated good C/N rate(10.2dB).

• 한국전자파학회논문지
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• 제22권3호
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• pp.371-379
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• 2011

최근의 다기능 레이더는 능동 위상 배열 안테나 구조를 이용하고 있다. 열약한 클러터 환경에서 표적을 탐지하기 위해서는 레이더 수신기의 동적 영역이 커야 한다. 능동 위상 배열 안테나 구조를 이용한 구조의 레이더는 SNR(Signal-to-Noise Ratio)를 향상시키지만, SFDR(Spurious Free Dynamic Range)은 개선되지 않는다. 본 논문에서는 높은 SFDR을 갖는 X-밴드 능동 위상 배열 레이더의 다채널 디지털 수신기를 설계하고 제작하였다. 32개의 T/R(Transmit/Receive) 모듈이 한 채널의 디지털 수신기와 연결되어 있다. 디지털 수신기내에 RF부, ADC부, 로컬 분배부 및 디지털 하향변환부가 존재하고, 한 개의 조립체 내에 2채널의 디지털 수신기가 포함되어 있다. 상용 FIFO 보드를 이용하여, 디지털 출력 신호에 대해, 디지털 수신기 주요 특성을 측정하였다. 제작된 디지털 수신기의 이득은 33 dB이고, SFDR은 81 dBc 이상이다.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2002년도 종합학술발표회 논문집 Vol.12 No.1
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• pp.44-48
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• 2002

This paper describes an adaptive signal processing of digital receiver with DDC(Digital Down Convertor), DDC is implemented by using NCO(Numerically Controlled Oscillator), digital low pass filter. for the passband sampling, we present the results of digital receiver simulation with DDC. We confirm that the low IP signal is converted to zero IF by DDC. DOA(Direction Of Arrival) estimation technique using MUSIC(Multiple SIgnal Classification) algorithm with high resolution is presented. We Cow that an accurate resolution of DOA depends on the input sampling number.

• 한국정보전자통신기술학회논문지
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• 제4권4호
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• pp.264-271
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• 2011

항공기의 계기착륙을 유도하는 시스템인 ILS(Instrument Landing System)는 1947년 ICAO(International Civil Aviation Organization)에서 국제표준으로 채택되어 현재는 상용시스템으로 출시되고 있다. 본 논문에서는 통합형 ILS 디지털 송수신 모듈의 설계방법을 제안하였다. 새롭게 제안한 것은 FPGA를 이용한 디지털 이중 AM 변복조기, 샘플링 클럭 생성을 위한 DDS(Direct Digital Synthesizer), DDC(Digital Down converter) 구조의 복조기, DSP 칩을 이용한 AM 스펙트럼 분석기의 디지털 설계 기법이다. 제안한 설계 방법의 유용성을 모듈 개발 및 실험을 통해 확인한 결과, 성능이 우수한 상용 시스템으로의 활용이 가능함을 확인하였다.

• 한국전자파학회논문지
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• 제25권3호
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• pp.282-288
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• 2014

본 논문에서는 디지털 레이더 수신기의 광대역 특성과 선형성을 확보하기 위해 동적 영역 파라미터를 중심으로 RF-수신단을 분석 및 설계하였다. 광대역 특성과 수신기의 동적 영역 개선을 위해 8.8~9.8 GHz의 광대역폭에서 저잡음 증폭기를 잡음원 매칭을 설계하여 잡음 지수를 최소화하였으며, 능동혼합기를 설계를 통한 수신기의 변환 이득 특성을 확보하여 RF-수신단의 선형성을 개선시켰다. 설계된 RF-수신단은 8.8~9.8 GHz의 광대역에서 이득 63 dB, 잡음 지수 1.2 dB을 얻었으며, RF-수신단의 동작영역은 75.8 dB의 특성을 나타내며, X-Band 디지털 레이더 수신기에 응용 가능함을 보였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권3호
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• pp.300-311
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• 2016

The analog-to-digital-converter-based (ADC-based) backplane receivers that consist of a front-end ADC followed by a digital equalizer are gaining more popularity in recent years, as they support more sophisticated equalization required for high data rates, scale better with fabrication technology, and are more immune to PVT variations. Unfortunately, designing an ADC-based receiver that meets tight power and performance budgets of high-speed backplane link systems is non-trivial as both front-end ADC and digital equalizer can be power consuming and complex when running at high speed. This paper reviews the state of art designs for the front-end ADC and digital equalizers to suggest implementation choices that can achieve high speed while maintaining low power consumption and complexity. Design-space exploration using system-level models of the ADC-based receiver allows through analysis on the impact of design parameters, providing useful information in optimizing the power and performance of the receiver at the early stage of design. The system-level simulation results with newer device parameters reveal that, although the power consumption of the ADC-based receiver may not comparable to the receivers with analog equalizers yet, they will become more attractive as the fabrication technology continues to scale as power consumption of digital equalizer scales well with process.

• 한국통신학회논문지
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• 제22권10호
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• pp.2329-2338
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• 1997

A conventional digital receiver sampled a baseband signal and processed it digitally for demodulation. But now we can sample at sufficiently high speed a wideband signal to take enough discrete data values due to the advent of economic high-speed ADC. With this technical background, a wideband frequency-division-multiplexed signal can be undersampled and channelized in digital domain by DFT analysis filter using the theory of polyphase. In this paper, we propose a new digital receiver which can digitally process the multichannel received signal by sampling at IF band, develop a mathematical theory and algorithm, and analyze the performance by using C-language simulaation. The proposed receiver can demodulate analog and digital FM signals.