• The Journal of Korean Academy of Prosthodontics
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• v.42 no.2
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• pp.192-209
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• 2004

Purpose : The purpose of this study was to evaluate the machining accuracy and consistency of implant/abutment/screw combination or internal connection type. Material and methods: In this study, each two randomly selected internal implant fixtures from ITI, 3i, Avana, Bicon, Friadent, Astra, and Paragon system were used. Each abutment was connected to the implant with 32Ncm torque value using a digital torque controller or tapping. All samples were cross-sectioned with grinder-polisher unit (Omnilap 2000 SBT Inc) after embeded in liquid unsaturated polyester (Epovia, Cray Valley Inc). Then optical microscopic and scanning electron microscopic(SEM) evaluations of the implant-abutment interfaces were conducted to assess quality of fit between the mating components. Results : 1) Generally, the geometry of the internal connection system provided for a precision fit of the implant/abutment into interface. 2) The most precision fit of the implant/abutment interface was provided in the case of Bicon System which has not screw. 3) The fit of the implant/abutment interface was usually good in the case of ITI, 3I and Avana system and the amount of fit of the implant/abutment interface was similar to each other. 4) The fit of the implant/abutment interface was usually good in the case of Friadent, Astra and Paragon system. The case of Astra system with the inclined contacting surface had the most Intimate contact among them. 5) Amount of intimate contact in the abutment screw thread to the mating fixture was larger in assembly with two-piece type which is separated screw from abutment such as Friadent, Astra and Paragon system than in that with one-piece type which is not seperated screw from abutment such as ITI, 3I and Avana system. 6) Amount of contact in the screw and the screw seat of abutment was larger in assembly of Friadent system than in asembly of Astra system of Paragon system. Conclusion: Although a little variation in machining accuracy and consistency was noted in the samples, important features of all internal connection systems were the deep, internal implant-abutment connections which provides intimate contact with the implant walls to resist micro-movement, resulting in a strong stable interface. From the results of this study, further research of the stress distribution according to the design of internal connection system will be required.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.6
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• pp.57-65
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• 2007

This paper presents the design of single phase PFC(Power Factor Correction) using a DSP(TMS320F2812). In order to realize the proposed boost PFC converter in average current mode control, the DSP requires the A/D sampling values for a line input voltage, a inductor current, and the output voltage of the converter. Because of a FET switching noise, these sampling values contain a high frequency noise and switching ripple. The solution of A/D sampling keeps away from the switching point. Because the PWM duty is changed from 5% to 95%, we can#t decide a fixed sampling time. In this paper, the three A/D converters of the DSP are started using the prediction algorithm for the FET ON/OFF time at every sampling cycle(40 KHz). Implemented A/D sampling algorithm with only one timer of the DSP is very simple and gives the autostart of these A/D converters. From the experimental result, it was shown that the power factor was about 0.99 at wide input voltage, and the output ripple voltage was smaller than 5 Vpp at 80 Vdc output. Finally the parameters and gains of PI controllers are controlled by serial communication with Windows Xp based PC. Also it was shown that the implemented PFC converter can achieve the feasibility and the usefulness.

• Progress in Medical Physics
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• v.14 no.3
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• pp.151-160
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• 2003

The application of more complex radiotherapy techniques using multileaf collimation (MLC), such as 3D conformal radiation therapy and intensity-modulated radiation therapy (IMRT), has increased the significance of verifying leaf position and motion. Due to thier reliability and empirical robustness, quality assurance (QA) of MLC. However easy use and the ability to provide digital data of electronic portal imaging devices (EPIDs) have attracted attention to portal films as an alternatives to films for routine qualify assurance, despite concerns about their clinical feasibility, efficacy, and the cost to benefit ratio. In this study, we developed method for daily QA of MLC using electronic portal images (EPIs). EPID availability for routine QA was verified by comparing of the portal films, which were simultaneously obtained when radiation was delivered and known prescription input to MLC controller. Specially designed two-test patterns of dynamic MLC were applied for image acquisition. Quantitative off-line analysis using an edge detection algorithm enhanced the verification procedure as well as on-line qualitative visual assessment. In conclusion, the availability of EPI was enough for daily QA of MLC leaf position with the accuracy of portal films.

• Journal of Biosystems Engineering
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• v.41 no.2
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• pp.126-137
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• 2016

Purpose: The overall objective of this study was to evaluate the vegetation fraction of soybeans, grown under different cropping conditions using an unmanned aerial vehicle (UAV) equipped with a red, green, and blue (RGB) camera. Methods: Test plots were prepared based on different cropping treatments, i.e., soybean single-cropping, with and without herbicide application and soybean and barley-cover cropping, with and without herbicide application. The UAV flights were manually controlled using a remote flight controller on the ground, with 2.4 GHz radio frequency communication. For image pre-processing, the acquired images were pre-treated and georeferenced using a fisheye distortion removal function, and ground control points were collected using Google Maps. Tarpaulin panels of different colors were used to calibrate the multi-temporal images by converting the RGB digital number values into the RGB reflectance spectrum, utilizing a linear regression method. Excess Green (ExG) vegetation indices for each of the test plots were compared with the M-statistic method in order to quantitatively evaluate the greenness of soybean fields under different cropping systems. Results: The reflectance calibration methods used in the study showed high coefficients of determination, ranging from 0.8 to 0.9, indicating the feasibility of a linear regression fitting method for monitoring multi-temporal RGB images of soybean fields. As expected, the ExG vegetation indices changed according to different soybean growth stages, showing clear differences among the test plots with different cropping treatments in the early season of < 60 days after sowing (DAS). With the M-statistic method, the test plots under different treatments could be discriminated in the early seasons of <41 DAS, showing a value of M > 1. Conclusion: Therefore, multi-temporal images obtained with an UAV and a RGB camera could be applied for quantifying overall vegetation fractions and crop growth status, and this information could contribute to determine proper treatments for the vegetation fraction.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.86-94
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• 2012

In this paper we propose a hardware architecture of high-speed CGH (computer generated hologram) generation processor, which particularly reduces the number of memory access times to avoid the bottle-neck in the memory access operation. For this, we use three main schemes. The first is pixel-by-pixel calculation rather than light source-by-source calculation. The second is parallel calculation scheme extracted by modifying the previous recursive calculation scheme. The last one is a fully pipelined calculation scheme and exactly structured timing scheduling by adjusting the hardware. The proposed hardware is structured to calculate a row of a CGH in parallel and each hologram pixel in a row is calculated independently. It consists of input interface, initial parameter calculator, hologram pixel calculators, line buffer, and memory controller. The implemented hardware to calculate a row of a $1,920{\times}1,080$ CGH in parallel uses 168,960 LUTs, 153,944 registers, and 19,212 DSP blocks in an Altera FPGA environment. It can stably operate at 198MHz. Because of the three schemes, the time to access the external memory is reduced to about 1/20,000 of the previous ones at the same calculation speed.

• Journal of Korea Game Society
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• v.7 no.3
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• pp.67-76
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• 2007

As the performance of game consoles is so highly progressed that services such as internet browsing become available on the consoles, the need for text input schemes on game consoles is rapidly raised. In this paper, we present a text input method of alphabet characters and several symbols using a gamepad, which is a widely used input device for most game consoles. Just like other text input methods using gamepad, our method allows users to enter texts by manipulating the gamepad with a user interface displayed on the screen of the console. A key idea of this paper is to present the user interface that is similar to the $4{\times}3$ keypad on mobile phones. The motivation of this idea is a principle that the experience of using a text input tool can be transferred to another tool that has similar interface. Another motivation is that the keyboard-based interface is too complex to be easily manipulated by simple input from a keypad, which is four orthogonal directions and several fire signals. Since most of keys on keypad of $4{\times}3$ keys are represented by a combination of two orthogonal directions, users feel easier in entering texts using keypad-based interface. We prove this argument in this paper by a user test of ten subjects. After about two experiment sessions, subjects reach 13 WPM in average, which proves that the proposed text input method enables much faster text input than the existing keyboard-based text input methods.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.5
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• pp.45-53
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• 2007

To recover transmitted signal perfectly at DTV receiver, we have to acquire carrier frequency synchronization to compensate pilot signal which located in wrong position and rotated phase. Also, we need a symbol timing synchronization to compensate sampling timing error. Conventionally, to synchronize symbol timing, we use Gardner's scheme which used in multi-level signal. Gardner's scheme is well known for its sampling the timing error signal from every symbol and it makes easy to detect and keep timing sync in multi-path channel. In this paper, to discuss the problem when the received power level is out of range and we cannot get synchronization information. With this problem, we use 2 step procedures. First, we put a received signal power compensation block before Garder's timing error detector. Second, adaptive loop filter to get a fast synchronization information and averaging loop filter's output value to reduce the amount of jitter after synchronization in PLL(Phased Locked Loop) circuit which is used to get a carrier frequency synchronization and symbol timing synchronization. Using the averaging value, we can estimate offset. Based on offset changing ratio, we can adapt adaptive loop filter to carrier frequency and symbol timing synchronization circuit.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.7A
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• pp.683-694
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• 2002

In this paper, a digital image compression codec using 2D DWT(Discrete Wavelet Transform) is designed using the FPGA technology for real time operation The implemented image compression codec using wavelet decomposition consists of a wavelet kernel part for wavelet filtering process, a quantizer/huffman coder for quantization and huffman encoding of wavelet coefficients, a memory controller for interface with external memories, a input interface to process image pixels from A/D converter, a output interface for reconstructing huffman codes, which has irregular bit size, into 32-bit data having regular size data, a memory-kernel buffer to arrage data for real time process, a PCI interface part, and some modules for setting timing between each modules. Since the memory mapping method which converts read process of column-direction into read process of the row-direction is used, the read process in the vertical-direction wavelet decomposition is very efficiently processed. Global operation of wavelet codec is synchronized with the field signal of A/D converter. The global hardware process pipeline operation as the unit of field and each field and each field operation is classified as decomposition levels of wavelet transform. The implemented hardware used FPGA hardware resource of 11119(45%) LAB and 28352(9％) ESB in FPGA device of APEX20KC EP20k600CB652-7 and mapped into one FPGA without additional external logic. Also it can process 33 frames(66 fields) per second, so real-time image compression is possible.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.12
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• pp.1336-1347
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• 1991

In this paper, The PC interface for packet terminal of ISDN is designed and implemented in order to build packet communication networks which share computer resources and exchange informations between computer in the ISDN environment. The PC interface for packet terminal of ISDN constitutes S interface handler part which controls functions of ISDN layer1 and layer 2, constitutes packet handler part which controls services of X.25 protocol in the packet level.Where, The function of ISDN layer1 provides rules of electrical and mechanical characteristics, services for ISDN layer 2. The function of ISDN layer 2 provides function of LAPD procedure, services for X.25 The X.25 specifies interface between DCE and DTE for terminals operrating in the packet mode. The S interface handler part is orfanized by Am 79C30 ICs manufactured by Advanecd Micro Devices. ISDN packet handler part is organiged by AmZ8038 for FIFO for the purpose of D channel. The common signal procedure for D channel is controlled by Intel's 8086 microprocessor. The S interface handler part is based on ISDN layer1,2 is controlled by mail box in order to communicate between layers. The ISDN packet handler part is based on module in the X.25 lebel. The communication between S interface handler part and ISDN packet handler part is organized by interface controller.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.9
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• pp.745-752
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• 2016

In the era of the Internet of Things, where all physical objects are connected to the Internet, we suggest a remote control system using a Raspberry Pi single-board computer with ZigBee, which can turn an indoor light-emitting diode (LED) and a multiple-tap on and off, and with a smart phone can control the brightness of the LED as well as an electronic door lock. By connecting an infrared (IR) transmitter module to the Raspberry Pi, we can control home appliances, such as an air conditioner, and we can also monitor indoor images, indoor temperatures, and illumination by using a smart phone app. We developed a method of finding out IR transmission codes required for remote-controllable appliances with an AVR micro-controller. We suggest a method to remotely open and shut an office door by novating the door lock. The brightness level of an LED (between 0 and 10) can be controlled through a PWM signal generated by an ATmega88 microcontroller. A mutiple-tap is controlled using an ATmega32, a photo-coupler, and a TRIAC. The signals for measured temperature and illumination are converted from analog to digital by using the ATtiny44A microcontroller transmitting to a Raspberry Pi through SPI communication. Then, we connect a camera to the CSI head of the Raspberry Pi. We can turn on the smart multiple-tap for a certain period of time, or we can schedule the multi-tap to turn on at a specific time. To reduce standby power, people usually pull out a power code from multiple-taps or turn off a switch. Our method helps people do the same thing with a smart phone, if they are away from home.