• 전기전자학회논문지
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• 제27권4호
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• pp.368-378
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• 2023

LED 매트릭스를 사용하는 차량용 헤드램프에서 LED의 디지털 제어는 I2C, SPI 등의 저가격 저속 직렬 버스를 사용하여 왔으나 헤드램프의 해상도가 증가하면서 LED 제어를 위해 전송해야 하는 데이터의 양이 너무 많아 제어 버스의 전송 능력을 초과하게 된다. 본 논문에서는 새로운 차량용 LED 매트릭스 헤드램프 제어 프로토콜인 HLCP(Headlamp LED Control Protocol)을 제안한다. 제안하는 프로토콜은 많은 LED를 하나의 명령어로 제어하는 명령어를 사용하여 I2C 버스를 거의 그대로 사용하면서도 훨씬 많은 LED를 제어할 수 있다. 제안하는 프로토콜을 수행하는 컨트롤러를 Verilog HDL로 구현 및 검증하였으며 시뮬레이션 결과 LED 매트릭스 헤드램프를 I2C나 SPI보다 효율적으로 제어할 수 있음을 확인하였다.

• 한국산업융합학회 논문집
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• 제26권6_2호
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• pp.1097-1108
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• 2023

Recently, demand for technology for energy economy and stable supply is increasing due to the increase in power demand of loads. The amount of DC power generation using new and renewable energy is noticeably increasing, and the use of DC power supplies is also increasing due to the increase in electric vehicles and digital loads. During parallel operation to increase the capacity of the power converter, the module bus method or the method using Can communication and serial communication has significant difficulties in smooth operation due to communication time delay for information sharing. Synchronization of information sharing of each power converter is essential for smooth parallel operation, and minimization of communication time delay is urgently needed as a way to overcome this problem. In this paper, a new communication method using pulse width information is proposed as a communication method specialized for parallel operation of power converters to compensate for the disadvantage of communication transmission delay in the existing system. The proposed communication method has the advantage of being easily implemented using the PWM and Capture function of the microcomputer. In addition, the DC/DC converter for DC distribution was verified through simulation and experiment, and it has the advantage of easy capacity expansion when applied to parallel operation of various types of power converters as well as DC/DC converters.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2004년도 ICCAS
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• pp.981-985
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• 2004

In this paper we designed the motor control IP Core and evaluate its quality from the viewpoint of IP reuse. The most attractive merit of this methodology, so called IP-based hardware design, is hardware reuse. Although various vendors designed hardware with the same specification and got the same functional results, all that IPs is not the same quality in the reuse aspect. As tremendous calls for SoC have been increased, associated research about IP quality standard, VSIA(Virtual Socket Interface Alliance) and STARC(Semiconductor Technology Academic Research Center), has been doing best to make the IP quality evaluation system. And they made what conforms to objective IP design standard. We suggest the methodology to evaluate our own designed motor control IP quality with this standard. To attain our goal, we designed motor control IP that could control the motor velocity and position with feedback compensation algorithm. This controller has some IP blocks : digital filter, quadrature decoder, position counter, motion compensator, and PWM generator. Each block's functionality was verified by simulator ModelSim and then its quality was evaluated. To evaluate the core, We use Vnavigator for lint test and ModelSim for coverage check. During lint process, We adapted the OpenMORE's rule based on RMM (Reuse Methodology Manual) and it could tell us our IP's quality in a manner of the scored value form. If it is high, its quality is also high, and vice versa. During coverage check ModelSim-SE is used for verifying how our test circuits cover designs. This objective methods using well-defined commercial coverage metrics could perform a quantitative analysis of simulation completeness. In this manner, We evaluated the designed motor control IP's quality from the viewpoint of reuse. This methodology will save the time and cost in designing SoC that should integrate various IPs. In addition to this, It can be the guide for comparing the equally specified IP's quality. After all, we are continuously looking forward to enhancing our motor control IP in the aspect of not only functional perfection but also IP reuse to prepare for the SoC-Compliant motor control IP design.