• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.4C
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• pp.337-342
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• 2010

In this paper, a new architecture for digit-parallel/bit-serial GF($2^m$) multiplier with low complexity is proposed. The proposed multiplier operates in polynomial basis of GF($2^m$) and produces multiplication results at a rate of one per D clock cycles, where D is the selected digit size. The digit-parallel/bit-serial multiplier is faster than bit-serial ones but with lower area complexity than bit-parallel ones. The most significant feature of the digit-parallel/bit-serial architecture is that a trade-off between hardware complexity and delay time can be achieved. But the traditional digit-parallel/bit-serial multiplier needs extra hardware for high speed. In this paper a new low complexity efficient digit-parallel/bit-serial multiplier is presented.

• Journal of Yeungnam Medical Science
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• v.7 no.2
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• pp.89-96
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• 1990

The purpose of this article was to determine the discriminant function analysis of the Korean Wechsler Intelligence Scale(KWIS) for 110 normal controls and 98 schizophrenics. Of special interest was to verify the clinical discriminant power of two subtests of the KWIS(Vacabulary and Digit Symbols) and Zung' s Self-rating Anxiety Scale(SAS). Four major hypotheses were postulated. The normal control group would show higher scores than the schizophrenics ; mean scores on both Vocabulary and Digit Symbol. The mean difference in Digit Symbol between the two groups would be greater than that in the Vacabulary. There would be no significant relation among Digit Symbol. Vacabulary. and Anxiety. The most powerful discriminant power would be expected from subtest of Digit Symbol. The mean discriminant scores were - 1.34425 for the control subjects. 1.34425 for the schizophrenics. The correctly discriminated percentage was 89.1% for the control subjects. 90.8% for the schizophrenics. From the findings it was concluded that both Digit Symbol and Vocabulary scales had strong diagnostic value but the former was more powerful than the latter. However. the Anxiety scales had less diagnostic value.

• Journal of Veterinary Clinics
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• v.34 no.1
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• pp.61-64
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• 2017

A 5-year-old, 6.2 kg male mixed dog was presented to local animal hospital with a 6-month history of swelling, pain, inflammation, and lameness in the 5th digit of right hind limb. And a 7-year-old, 2.7 kg male Maltese dog was also presented to animal hospital with a 2-month history of nail deformities in the 5th digit of left hind limb. Abnormal growth or degeneration of the distal phalanges was observed at the 5th digit of hind limb in two dogs using radiographic examination. The masses in the digit were excised completely under local anesthesia. On histological examination of the digit masses, large well-circumscribed, unencapsulated round or irregular cystic neoplasms with/without inflammation were occupied in or adjacent area of the distal phalanx. These cysts were lined by stratified squamous epithelium that occasionally had a prominent granular cell layer. Based on the history, clinical signs, radiographic, gross and histopathologic features, these cases were diagnosed as nailbed epithelial inclusion cysts in the digit of dogs.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.140-143
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• 2000

소형화와 안전성에서 보다 더 진보된 ECC( Elliptic Curve Cryptography) 암호화 알고리즘의 하드웨어적 구현을 제안한다. Basis는 VLSI 구현에 적합한 standard basis이며 m=193 ECC 승산기 회로를 설계하였다. Bit-Parallel 구조를 바탕으로 Digit-Serial/Bit-Parallel 방법으로 구현하였다. 제안된 구조는 VHDL 및 SYNOPSYS로 검증되었다.

• MALSORI
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• no.43
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• pp.179-188
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• 2002

Improving the recognition performance of connected digit telephone speech still remains a problem to be solved. As a basic study for it, this paper analyzes the variation of feature parameters of Korean digit telephone speech according to channel distortion. As a feature parameter for analysis and recognition MFCC is used. To analyze the effect of telephone channel distortion depending on each call, MFCCs are first obtained from the connected digit telephone speech for each phoneme included in the Korean digit. Then CMN, RTCN, and RASTA are applied to the MFCC as channel compensation techniques. Using the feature parameters of MFCC, MFCC+CMN, MFCC+RTCN, and MFCC+RASTA, variances of phonemes are analyzed and recognition experiments are done for each case. Experimental results are discussed with our findings and discussions

• MALSORI
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• no.45
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• pp.47-61
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• 2003

In this paper, we consider the implementation of connected digit recognition system and the several approaches to improve its performance. To implement efficiently the fixed or variable length digit recognition system, finite state network (FSN) is required. We merge the word network algorithm that implements the FSN with one pass dynamic programming search algorithm that is used for general speech recognition system for fast search. To find the efficient modeling of digit recognition system, we perform some experiments along the various conditions to affect the performance and summarize the results.

• Journal of Electrical Engineering and Technology
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• v.13 no.2
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• pp.943-952
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• 2018

This paper presents a new type of absolute rotary encoder system based on the affine n-digit N-ary gray code. A brief comparison of the existing encoder systems is carried out in terms of resolution, encoding and decoding principles and number of sensor heads needed. Using the proposed method, two different types of encoder disks are designed, namely, color-coded disk and grayscale coded disk. The designed coded disk pattern is used to manufacture 3 digit 3 ary and 2 digit 5 ary grayscale coded disks respectively. The manufactured disk is used with the light emitter and photodetector assembly to design the entire encode system. Experimental analysis is done on the designed prototype with LabVIEW platform for data acquisition. A comparison of the designed system is done with the traditional binary gray code encoder system in terms of resolution, disk diameter, number of tracks and data acquisition system. The resolution of the manufactured system is 3 times higher than the conventional system. Also, for a 5 digit 5 ary coded encoder system, a resolution approximately 100 times better than the conventional binary system can be achieved. In general, the proposed encoder system gives $(N/2)^n$ times better resolution compared with the traditional gray coded disk. The miniaturization in diameter of the coded disk can be achieved compared to the conventional binary systems.

• Journal of KIISE:Software and Applications
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• v.31 no.12
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• pp.1581-1590
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• 2004

We present a robust off-line method recognizing handwritten digits by only using stroke direction codes as a feature of handwritten digits. This method makes general 8-direction codes for an input digit and then has the multi-layered neural networks learn them and recognize each digit. The 8-direction codes are made of the thinned results of each digit through SOG*(Improved Self-Organizing Graph). And the usage of these codes simplifies the complex steps processing at least two features of the existing methods. The experimental result shows that the recognition rates of this method are constantly better than 98.85% for any images in all digit databases.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.2
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• pp.37-44
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• 2001

In this paper, an efficient architecture for the ECC multiplier in GF(2") is proposed. We give a design example for the irreducible trinomials $x_{193}\;+\;x_{15}\;+\;1$. In hardware implementations, it is often desirable to use the irreducible trinomial equations. A digit-serial multiplier with a digit size of 32 is proposed, which has more advantages than the 193bit serial LFSR architecture. The proposed multiplier is verified with a VHDL description using an elliptic curve addition. The elliptic curve used in this implementation is defined by Weierstrass equations. The measured results show that the proposed multiplier it 0.3 times smaller than the bit-serial LFSR multiplier.lier.

• The KIPS Transactions:PartA
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• v.15A no.3
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• pp.161-166
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• 2008

In this paper, an efficient digit-serial systolic array is proposed for multiplication in finite field GF($2^m$) using the polynomial basis representation. The proposed systolic array is based on the most significant digit first (MSD-first) multiplication algorithm and produces multiplication results at a rate of one every "m/D" clock cycles, where D is the selected digit size. Since the inner structure of the proposed multiplier is tree-type, critical path increases logarithmically proportional to D. Therefore, the computation delay of the proposed architecture is significantly less than previously proposed digit-serial systolic multipliers whose critical path increases proportional to D. Furthermore, since the new architecture has the features of a high regularity, modularity, and unidirectional data flow, it is well suited to VLSI implementation.