• The monthly packaging world
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• s.345
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• pp.71-78
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• 2022

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.12S
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• pp.1237-1241
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• 2003

In this paper, we report a novel RF-MEMS packaging technology with lightweight, small size, and short electric path length. To achieve this goal, we used the ultra thin silicon substrate as a packaging substrate. The via holes lot vortical feed-through were fabricated on the thin silicon wafer by wet chemical processing. Then, via holes were filled and micro-bumps were fabricated by electroplating. The packaged RF device has a reflection loss under 22 〔㏈〕 and a insertion loss of -0.04∼-0.08 〔㏈〕. These measurements show that we could package the RF device without loss and interference by using the vertical feed-through. Specially, with the ultra thin silicon wafer we can realize of a device package that has low-cost, lightweight and small size. Also, we can extend a 3-D packaging structure by stacking assembled thin packages.

• Journal of the Microelectronics and Packaging Society
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• v.10 no.1
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• pp.31-38
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• 2003

In the current electronic technology atmosphere, MEMS (Microelectromechanical System) technology is regarded as one of promising device manufacturing technologies to realize market-demanding device properties. In the packaging of MEMS devices, the packaged structure must maintain hermeticity to protect the devices from a hostile atmosphere during their operations. For such MEMS device vacuum packaging, we introduce the LTCC (Low temperature Cofired Ceramic) packaging technology, in which embedded passive components such as resistors, capacitors and inductors can be realized inside the package. The technology has also the advantages of the shortened length of inner and surface traces, reduced signal delay time due to the multilayer structure and cost reduction by more simplified packaging processes owing to the realization of embedded passives which in turn enhances the electrical performance and increases the reliability of the packages. In this paper, the leakage rate of the LTCC package having several interfaces was measured and the possibility of LTCC technology application to MEMS devices vacuum packaging was investigated and it was verified that improved hermetic sealing can be achieved for various model structures having different types of interfaces (leak rate: stacked via; $4.1{\pm}1.11{\times}10^{-12}$/ Torrl/sec, LTCC/AgPd/solder/Cu-tube; $3.4{\pm}0.33{\times}10^{-12}$/ Torrl/sec). In real application of the LTCC technology, the technology can be successfully applied to the vacuum packaging of the Infrared Sensor Array and the images of light-up lamp through the sensor way in LTCC package structure was presented.

• Journal of the Microelectronics and Packaging Society
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• v.29 no.2
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• pp.99-105
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• 2022

As the chip size gets smaller, the width of the electrode line is also fine, and the density of interconnections is increasing. As a result, RC delay is becoming a problem due to the difference in resistance between the capacitor layer and the electrical conductivity layer. To solve this problem, the development of electrodes with high electrical conductivity and dielectric materials with low dielectric constant is required. In this study, we developed low dielectric ink by mixing commercial PSR which protect PCB's circuits from external factors and PI with excellent thermal property and low-k characteristics. As a result, the ink mixture of PSR and PI 10:3 showed the best results, with a dielectric constant of about 2.6 and 2.37 at 20 GHz and 28 GHz, respectively, and dielectric dissipation was measured at about 0.022 and 0.016. In order to verify the applicability of future applications, various line-width transmission lines produced on Teflon were evaluated, and as a result, the loss of transmission lines using low dielectric ink mixed with PI was 0.12 dB less on average in S21 than when only PSR was used.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.3
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• pp.1-6
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• 2013

3D integrated circuit(IC) technology with TSV(through Si via) liquid cooling system is discussed. As a device scales down, both interconnect and packaging technologies are not fast enough to follow transistor's technology. 3D IC technology is considered as one of key technologies to resolve a device scaling issue between transistor and packaging. However, despite of many advantages, 3D IC technology suffers from power delivery, thermal management, manufacturing yield, and device test. Especially for high density and high performance devices, power density increases significantly and it results in a major thermal problem in stacked ICs. In this paper, the recent studies of TSV liquid cooling system has been reviewed as one of device cooling methods for the next generation thermal management.

• The monthly packaging world
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• s.149
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• pp.75-81
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• 2005

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2006.02a
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• pp.77-85
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• 2006

• The monthly packaging world
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• s.255
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• pp.61-67
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• 2014

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.04a
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• pp.29-33
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• 2000

MEMS, Micro Electro-Mechanical Systems, present one of the greatest advanced packaging challenges of the next decade. Historically hybrid technology, generally thick film, provided sensors and actuators while integrated circuit technologies provided the microelectronics for interpretation and control of the sensor input and actuator output. Brought together in MEMS these technical fields create new opportunities for miniaturization and performance. Integrated circuit processing technologies combined with hybrid design systems yield innovative sensors and actuators for a variety of applications from single crystal silicon wafers. MEMS packages, far more simple in principle than today's electronic packages, provide only physical protection to the devices they house. However, they cannot interfere with the function of the devices and often must actually facilitate the performance of the device. For example, a pressure transducer may need to be open to atmospheric pressure on one side of the detector yet protected from contamination and blockage. Similarly, an optical device requires protection from contamination without optical attenuation or distortion being introduced. Despite impediments such as package standardization and complexity, MEMS markets expect to double by 2003 to more than ＄9 billion, largely driven by micro-fluidic applications in the medical arena. Like the semiconductor industry before it. MEMS present many diverse demands on the advanced packaging engineering community. With focused effort, particularly on standards and packaging process efficiency. MEMS may offer the greatest opportunity for technical advancement as well as profitability in advanced packaging in the first decade of the 21st century! This paper explores MEMS packaging opportunities and reviews specific technical challenges to be met.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.09a
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• pp.147-164
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• 2001

1. "MLS", state of the art MCM-D wiring substrate. 2. High pin-count LSl assembly. 3. Higher speed needs higher packaging density. 4. Wiring substrate, the key of LSl packaging device. 5. "Inter-Layer Transferability", a new index for the performance of wiring substrates. 6. "MLTF package", a core-less flexible package for high pin-count LSl.