• 제어로봇시스템학회:학술대회논문집
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• 1994.10a
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• pp.7-12
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• 1994

This paper describes an outline of pseudorandom M-sequence and its applications to measurement and control engineering. At first, generation and properties of M-sequence is briefly described and then its applications to delay time measurement, information transmission by use of M-array, two dimensional positioning, fault detection of logical circuit, fault detection of RAM, linear and nonlinear system identification.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.6
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• pp.1146-1151
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• 2011

There are two methods for train control in information transmission by using track circuit system and installing wayside transmitter. Information signal is transmitted to the on-board antenna by using rails. Continuous information about train intervals, speed and route is received by on-board antenna in AF track circuit system. The information signal is included with carrier wave and received by magnetic coupling in the on-board antenna. Therefore, it is important to define standard current level in the AF track circuit system. When current flowed to rails is low, magnetic sensors are not operated by decreasing magnetic field intensity. Hence, SNR is decreased because electric field intensity is decreased. When the SNR is decreased, there is the serious influence of noise upon demodulation. So, the frequency of information signal is not extracted in frequency response. Thus, it is possible to happen to train accident and delay as the information signal is not analyzed in the on-board antenna. In this paper, standard energy density is calculated by using Parseval's theory in UM71c track circuit. Hence, detection time of information signal is presented.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.6
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• pp.28-36
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• 1998

We have proposed a new non-inverting SOI buffer circuit for the high speed operation at low supply voltage. The body biases of main MOS devices in the proposed circuit are controlled dynamically via subsidiary MOS device connected efficiently to the body terminal. We showed current derivability of the body controlled devices obtained by device simulation and compared with that of conventional SOI devices. Delay time characteristics of the buffer circuit were analyzed by SPICE simulation and compared with those of conventional SOI CMOS buffer circuits. Delay time reduction of the SOI buffer over conventional SOI CMOS buffer with same area is about 36 % at $V_{S}$=1.2 V and $C_{L}$=2 pF. pF.

• Proceedings of the KIEE Conference
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• 2003.07c
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• pp.1852-1854
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• 2003

In manufacturing processes, various and suitable pulse shapes are required for the purpose of material processing. In order to make various pulse shapes with variable pulse length and high duty cycle, We have fabricated the power supply consisting 6 SCRs and the Pulse Forming Network(PFN) with the precise delay time control. So our control system has three switching circuits, 3 mesh PFN, and simmer circuit. In addition, we have designed and fabricated the PIC one-chip microprocessor(16F877) to control the delay time of sequential switching.

• The Transactions of the Korean Institute of Power Electronics
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• v.9 no.3
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• pp.275-284
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• 2004

This paper discusses how to control the compensation voltages in dynamic voltage restorers (DVR). On analyzing the power circuit of a DVR system, control limitations and control targets are presented for the voltage compensation in DVRs. Based on the preceded power stage analysis, a novel controller for the compensation voltages of DVRs is proposed by a feed forward control scheme. This paper discusses also the time delay problems in the control system of DVRs. Digitally controlled DVR systems normally have control delay at amount of one sampling time of the control system and a half of the switching period of the DVR inverter. The control delay in digital controllers increases the dimension of the system transfer function one degree higher, which makes the control system more complicate and more unstable. This paper proposes a guide line to design the control gain, appropriate output filter parameters and inverter switching frequency for DVRs with digital controllers. Proposed theory is verified by an experimental DVR system with a full digital controller.

• Journal of Biomedical Engineering Research
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• v.25 no.6
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• pp.565-573
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• 2004

In this paper, we proposed a heart activity control model for simulation of the aortic sinus baroreceptor, which was the most representative baroreceptor sensing the variance of pressure in the cardiovascular system. And then, the heart activity control model composed electric circuit model of the cardiovascular system with baroreflex control and time delay sub-model to observe the effect of time delay in heart period and stroke volume under the regulation of baroreflex in the aortic sinus. The mechanism of time delay in the heart activity baroreflex control model is as follows. A control function is conduct sensing pressure information in the aortic sinus baroreceptor to transmit the efferent nerve through central nervous system. As simulation results of the proposed model, we observed three patterns of the cardiovascular system variability by the time delay. First of all, if the time delay over 2.5 second, aortic pressure and stroke volume and heart rate was observed non-periodically and irregularly. However, if the time delay from 0.1 second to 0.25 second, the regular oscillation was observed. And then, if time delay under 0.1 second, then heart rate and aortic pressure-heart rate trajectory were maintained in stable state.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.10a
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• pp.459-461
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• 2022

One of the big differences between Network-on-Chip (NoC) and the existing parallel processing system based on an off-chip network is that data packet routing is performed using a centralized control scheme. In such an environment, the best-effort packet routing problem becomes a real-time assignment problem in which data packet arriving time and processing time is the cost. In this paper, the Hungarian algorithm, a representative computational complexity reduction algorithm for the linear algebraic equation of the allocation problem, is implemented in the form of a hardware accelerator. As a result of logic synthesis using the TSMC 0.18um standard cell library, the area of the circuit designed through case analysis for the cost distribution is reduced by about 16% and the propagation delay of it is reduced by about 52%, compared to the circuit implementing the original operation sequence of the Hungarian algorithm.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.10
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• pp.1487-1493
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• 2013

A new simple control method for active power filter, which can realize the complete compensation of harmonics is proposed. In the proposed scheme, a model-based digital current control strategy is presented. The proposed control system is designed and implemented in a form referred to as internal model control structure. This method provides a convenient way for parameterizing the controller in term of the nominal system model, including time-delays. As a result, the resulting controller parameters are directly set based on the power circuit parameters, which make tuning of the controllers straightforward task. In the proposed control algorithm, overshoots and oscillations due to the computation time delay is prevented by explicit incorporating of the delay in the controller transfer function. In addition, a new compensating current reference generator employing resonance model implemented by a DSP(Digital Signal Processor) is introduced. Resonance model has an infinite gain at resonant frequency, and it exhibits a band-pass filter. Consequently, the difference between the instantaneous load current and the output of this model is the current reference signal for the harmonic compensation.

• Journal of Korea Society of Digital Industry and Information Management
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• v.16 no.2
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• pp.1-9
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• 2020

Many cryptographic and error control coding algorithms rely on finite field GF(2m) arithmetic. Hardware implementation of these algorithms needs an efficient realization of finite field arithmetic operations. Finite field multiplication is complicated among the basic operations, and it is employed in field exponentiation and division operations. Various algorithms and architectures are proposed in the literature for hardware implementation of finite field multiplication to achieve a reduction in area and delay. In this paper, a low area and delay efficient semi-systolic multiplier over finite fields GF(2m) using the modified Montgomery modular multiplication (MMM) is presented. The least significant bit (LSB)-first multiplication and two-level parallel computing scheme are considered to improve the cell delay, latency, and area-time (AT) complexity. The proposed method has the features of regularity, modularity, and unidirectional data flow and offers a considerable improvement in AT complexity compared with related multipliers. The proposed multiplier can be used as a kernel circuit for exponentiation/division and multiplication.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.9
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• pp.111-117
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• 1998

This paper presents a polarity changing method without dead time of a cycloconverter with an LC resonant circuit. According to the proposed method, dead time to prevent short circuit for the polarity changing is not required. Therefore the delay of control and the harmonic components of output currents can be decreased. And the proposed method can be expanded for the other natural commutated cycloconverters of noncirculating current type. In this paper, the switching method of the proposed polarity changing without dead time is studied, and in order to confirm the validity of the proposed method the experiment is carried out with a cycloconverter with an LC resonant circuit.