• Title/Summary/Keyword: delay cell

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Node Architecture and Cell Routing Strategies for ATM Applications in WDM Multihop Networks (WDM 다중홉 망에서 ATM 응용을 위한 노드 구조 및 셀 라우팅 기법)

  • Lee, Ho-Suk;Lee, Cheong-Hun;So, Won-Ho;Kwon Hyeok-Jung;Kim, Yeong-Cheon
    • Journal of the Korean Institute of Telematics and Electronics S
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    • v.35S no.11
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    • pp.44-52
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    • 1998
  • In this paper, we proposed a node architecture and cell routing strategies for ATM applications in WDM multihop networks. The proposed node architecture employs the optical delay loop for storing the cell which is failed in out-link contention. This optical delay loop allows the delay of one cell without the electro-optic conversion. Therefore, we can get the advantages of S&F(Store-and-Forward) routing in Deflection-based all-optical networks. To support the ATM applications efficiently. we considered the transmission priority of ATM cell so that high priority cell can be transmitted with lower loss and shorter delay than low priority one. Two kinds of routing strategies are designed for this architecture: Scheme-Ⅰand Scheme-Ⅱ. Scheme-Ⅰapplies S&F routing to high cell and Deflection routing to low cell, i.e., high cells are routed along the shortest path based on S&F routing, but low cells are deflected or lost. Schem-Ⅱ is similar to Scheme-Ⅰexcept that low cells can occupy the optical loop if it is available. This Scheme-Ⅱ increases the utilization of network resources without decreasing the throughput of high cell by reducing the low cell loss rate when traffic load is low. Simulation results show that our routing strategies have better performance than conventional ones under non-uniform traffic as well as uniform traffic.

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The enhance driority transfer control mechanism for multimedia communication in ATM networks (ATM 망에서 멀티미디어 통신을 위한 EPT(enhanced priority transfer)제어기법)

  • 박성호;박성곤;최승권;조용환
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.23 no.9A
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    • pp.2249-2257
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    • 1998
  • In this paper, we propose the enhanced priority control algorithm that adaptively controls the cell service ratio according to the relative cell occupancy ratio of buffer. The asynchronous transfer mode (ATM) provides the means to support various multimedia services in broadband networks. To support multimedia services, various data traffics of different priorities should be controlled effectively. And also it needs congestion control functions required in the netowrk to carry out the control operation. To accomplish this in a flexible and effective manner, priority classes for the different services ar ecommonly used. The proposed enhanced priority control mechanism have two service calsses of the delay sensitive class and the loss sensitive class. The simulation results show that te proposed control mechanism improves the QoS, the charateristics of cell loss probability and mean cell delay time, by selecting propeor relativ ecell occupancy ratio of buffer and the average arrival rate.

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Design of In-Memory Computing Adder Using Low-Power 8+T SRAM (저 전력 8+T SRAM을 이용한 인 메모리 컴퓨팅 가산기 설계)

  • Chang-Ki Hong;Jeong-Beom Kim
    • The Journal of the Korea institute of electronic communication sciences
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    • v.18 no.2
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    • pp.291-298
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    • 2023
  • SRAM-based in-memory computing is one of the technologies to solve the bottleneck of von Neumann architecture. In order to achieve SRAM-based in-memory computing, it is essential to design efficient SRAM bit-cell. In this paper, we propose a low-power differential sensing 8+T SRAM bit-cell which reduces power consumption and improves circuit performance. The proposed 8+T SRAM bit-cell is applied to ripple carry adder which performs SRAM read and bitwise operations simultaneously and executes each logic operation in parallel. Compared to the previous work, the designed 8+T SRAM-based ripple carry adder is reduced power consumption by 11.53%, but increased propagation delay time by 6.36%. Also, this adder is reduced power-delay-product (PDP) by 5.90% and increased energy-delay- product (EDP) by 0.08%. The proposed circuit was designed using TSMC 65nm CMOS process, and its feasibility was verified through SPECTRE simulation.

Cell Association Scheme for Uplink Heterogeneous Cellular Networks (이기종 셀룰러 네트워크에서의 상향 링크 셀 접속 기법)

  • Lee, Hyung Yeol;Sang, Young Jin;Park, Jin Bae;Kim, Kwang Soon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.38A no.5
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    • pp.393-400
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    • 2013
  • In conventional single-tier networks, downlink based association is the best association scheme for the uplink association because all macro base stations have the same physical specification. However, in uplink heterogeneous cellular networks, a downlink based cell association cannot be the best for uplink any more because of the difference of physical specification between the different base station. In this paper, we will propose a uplink based cell association scheme, and devise performance metric for describing a uplink performance in heterogeneous cellular networks. Then, we will discuss the necessity of the uplink based association by observing outage probability, delay constraint outage probability, delay constraint outage capacity.

Thermal Aware Buffer Insertion in the Early Stage of Physical Designs

  • Kim, Jaehwan;Ahn, Byung-Gyu;Kim, Minbeom;Chong, Jongwha
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.12 no.4
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    • pp.397-404
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    • 2012
  • Thermal generation by power dissipation of the highly integrated System on Chip (SoC) device is irregularly distributed on the intra chip. It leads to thermal increment of the each thermally different region and effects on the propagation timing; consequently, the timing violation occurs due to the misestimated number of buffers. In this paper, the timing budgeting methodology considering thermal variation which contains buffer insertion with wire segmentation is proposed. Thermal aware LUT modeling for cell intrinsic delay is also proposed. Simulation results show the reduction of the worst delay after implementing thermal aware buffer insertion using by proposed wire segmentation up to 33% in contrast to the original buffer insertion. The error rates are measured by SPICE simulation results.

A DELAY DYNAMIC MODEL FOR HIV INFECTED IMMUNE RESPONSE

  • BERA, S.P.;MAITI, A.;SAMANTA, G.P.
    • Journal of applied mathematics & informatics
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    • v.33 no.5_6
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    • pp.559-578
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    • 2015
  • Human Immune Deficiency Virus (or simply HIV) induces a persistent infection that leads to AIDS causing death in almost every infected individual. As HIV affects the immune system directly by attacking the CD4+ T cells, to exterminate the infection, the natural immune system produces virus-specific cytotoxic T lymphocytes(CTLs) that kills the infected CD4+ T cells. The reduced CD4+ T cell count produce reduced amount of cytokines to stimulate the production of CTLs to fight the invaders that weakens the body immunity succeeding to AIDS. In this paper, we introduce a mathematical model with discrete time-delay to represent this cell dynamics between CD4+ T cells and the CTLs under HIV infection. A modified functional form has been considered to describe the infection mechanism. Characteristics of the system are studied through mathematical analysis. Numerical simulations are carried out to illustrate the analytical findings.

Sequential Paging under Delay Bound for Next Generation Mobile Systems (차세대 이동통신에서의 지연을 고려한 순차적 페이징)

  • Lee, Chae-Yong;Ku, Sang-Hoon
    • Korean Management Science Review
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    • v.23 no.3
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    • pp.13-25
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    • 2006
  • To reduce the signaling tost of paging in mobile communication, sequential paging schemes are proposed by partitioning a location area into several paging areas such that each area is paged sequentially. Necessary conditions for the optimal partition of cells with delay bound are examined by considering the mobiles location probability at each cell. The Optimal Cell Partitioning (OCP) is proposed based on the necessary conditions and the fathoming rule which trims off the unnecessary solution space and expedite the search process. Two Heuristics, BSG and BNC are also presented to further increase the computational efficiency in real-world paging scheme for the next generation mobile systems. The effectiveness of the 1)reposed paging schemes is illustrated with computational results. The Heuristic BSG that performs the search in the most promising solution group outperforms the best existing procedure with the 6-69% gain in paging cost in problems with 100 cells.

A Medium Access Control Protocol for rt- VBR Traffic in Wireless ATM Networks

  • Lim, In-Taek
    • Journal of information and communication convergence engineering
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    • v.5 no.1
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    • pp.29-34
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    • 2007
  • This paper proposes a MAC protocol for real-time VBR (rt-VBR) services in wireless ATM networks. The proposed protocol is characterized by a contention-based mechanism of the reservation request, a contention-free polling scheme for transferring the dynamic parameters, and a priority scheme of the slot allocation. The design objective of the proposed protocol is to guarantee the real-time constraint of rt-VBR traffic. The scheduling algorithm uses a priority scheme based on the maximum cell transfer delay parameter. The wireless terminal establishes an rt-VBR connection to the base station with a contention-based scheme. The base station scheduler allocates a dynamic parameter minislot to the wireless terminal for transferring the residual lifetime and the number of requesting slots as the dynamic parameters. Based on the received dynamic parameters, the scheduler allocates the uplink slots to the wireless terminal with the most stringent delay requirement. The simulation results show that the proposed protocol can guarantee the delay constraint of rt-VBR services along with its cell loss rate significantly reduced.

A Study on the Improvement of Real-Time Traffic QoS using the Delay Guarantee Queue Service Discipline of End-to-End (종단간 지연 큐 서비스 방식을 이용한 실시간 트래픽 QoS 개선에 관한 연구)

  • 김광준;나상동
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.6 no.2
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    • pp.236-247
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    • 2002
  • We propose a cell-multiplexing scheme for the real-time communication service in ATM network and a new service discipline guarantee end-to-end delay based on pseudo-isochronous cell switching. The proposed scheme consists of two level frame hierarchy, upper and lower frame, which is used to assign the bandwidth and to guarantee the requested delay bound, respectively. Since the Proposed algorithm employs two level frame hierarchy, it can overcome the coupling problem which is inherent to the framing strategy It can be comparatively reduce the complexity, and still guarantee the diverse delay bounds of end-to-end. Besides, it consists of two components, traffic controller and scheduller, as the imput traffic description model and regulates the input traffic specification. The function of the traffic controller is to shape real -time traffic to have the same input pattern at every switch along the path. The end-to-end delay is bounded by the scheduller which can limit the delay variation without using per-session jitter controllers, and therefore it can decrease the required buffer size. The proposed algorithm can support the QoS's of non-real time traffic as well as those of real time traffic.

LOS/LOC Scan Test Techniques for Detection of Delay Faults (지연고장 검출을 위한 LOS/LOC 스캔 테스트 기술)

  • Hur, Yongmin;Choe, Youngcheol
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.14 no.4
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    • pp.219-225
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    • 2014
  • The New efficient Mux-based scan latch cell design and scan test of LOS/LOC modes are proposed for detection of delay faults in digital logic circuits. The proposed scan cell design can support LOS(Launch-off-Shift) and LOC(Launch-off-Capture) tests with high fault coverage and low scan power and it can alleviate the problem of the slow selector enable signal and hold signal by supporting the logic capable of switching at the operational clock speeds. Also, it efficiently controls the power dissipation of the scan cell design during scan testing. Functional operation and timing simulation waveform for proposed scan hold cell design shows improvement in at-speed test timing in both test modes.