• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.132-141
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• 1996

The pixelated phase grating has been studied as a kind of diffraction gratings splitting and input beam into multiple spots. It consists of regular size cells which produce phase delays, and each cell provokes the phase delay up to sixteen levels. We have compared and analyzed the characteristics of multi-level phase gratings, laying streess on efficiency and resulted pattern. Experimental resutls obtained form fabricated grating have been presented, and the real-time method using a liquid-crystal spatial light modulator has been demonstrated through experiments. Gratings making meams with specific intensities have been designed and optical images have been generated by them. In order to specific intensities have been designed and optical images have been genrated by them. In order to decide the phase delay of each cell, optimization conditon consists of diffraction efficiency and target values. One period of phase gratings fabricated with surface relief was less than 256${\mu}m{\times}256{\mu}m$ and size of each cell was 1${\mu}m{\times}1{\mu}m$ surface relief grating has been made by coating photoresist on the glass plate, writing information pattern by Ar laser and developing it. in the experiment for real-tiem processing liquid-crystal display of epson video projector has been used.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.5
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• pp.479-484
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• 2016

In this paper, a design of DC level shifter transmitting and receiving control and data signal which have various DC level through daisy chain interface between master IC and slave is introduced in the cell voltage monitoring (CVM). Circuit designed with a latch structure have a function to operate in high speed and for output of variable DC level through transmission gate. As a result of the simulation and the measurement, it was confirmed that control and data signal could be transferred according to the change of DC level from 0V to 30V. Delay time was measured about 170ns. but, it was considered as a negligible tolerance due to a parasitic capacitance of measuring probe and test board.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.11
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• pp.960-965
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• 2015

In this paper, a coupled line directional coupler using an LUC(Low-pass filter Unit Cell) of artificial transmission line is presented. The conventional coupled line coupler is limited in length by the ${\lambda}/4$ transmission line while the proposed coupling structure is implemented smaller than $90^{\circ}$ by inserting the phase delay line between two coupled line, reduced in physical size by configuring a phase delay line with an LUC having the characteristics of a typical transmission line in a particular frequency. A coupler having -10 dB coupling factor at the center frequency of 700 MHz is designed, fabricated. The measured result agrees well with that of conventional one. The length of the fabricated coupled line coupler has about 45 % in length compared to the conventional one.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39A no.11
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• pp.682-689
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• 2014

Due to explosive growth of mobile data traffic, many kind of techniques based on small cell is proposed as solution for phenomenon. However, those techniques essentially demands increase of backhaul capacity and causes performance degradation if not satisfied. Based on that, the approach applying the storage capacity in place of backhaul capacity, which is known as femto-caching, is proposed to reduce data downloading delay of users in system. In this paper, we expanded previous research by proposing file placement strategy with distribution of user position, which is more practical scenario. Simulation results verify that our proposed scheme has better performance gains mainly because when coverage of helpers are overlapped, users get more opportunity to connect various helpers which enables users to download a variety kind of files from helpers, not base station.

• Journal of Internet Computing and Services
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• v.17 no.6
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• pp.25-31
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• 2016

Recently, with greatly improving the wireless communication technology, new services are created using smart sensors, i.e., machine-to-machine (M2M) and Internet of Things (IoT). In this paper, we propose a novel IoT device (IoTD) personalization method that adopt Small-cell Access Points (SAPs) to control IoTDs using user equipments (UEs), e.g., smart phones and tablet PC, from service users. First, we introduce a system architecture that consists of UE, IoTD, and SAP and propose the IoTD personalization method with two procedures, i.e., IoTD profile registration procedure and IoTD control procedure. Finally, through simulations, we evaluated the system performance of the proposed scheme and it is shown that the proposed scheme outperforms the conventional scheme in terms of the packet delay, packet loss probability, and normalized throughput.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.64 no.4
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• pp.315-320
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• 2015

Proposal algorithm in this paper introduced cells, units of router group, for distributed processing of previous genetic algorithm. This paper presented ways to reduce search delay time of overall network through cell-based genetic algorithm. As a result of performance analysis comparing with existing genetic algorithm through experiments, the proposal algorithm was verified superior in terms of costs and delay time. Furthermore, time for routing an alternative path was reduced in proposal algorithm, in case that a network was damaged in existing optimal path algorithm, Dijkstra algorithm, and the proposal algorithm was designed to route an alternative path faster than Dijkstra algorithm, as it has a 2nd shortest path in cells of the damaged network. The study showed that the proposal algorithm can support routing of alternative path, if Dijkstra algorithm is damaged in a network.

• Journal of the Korean Operations Research and Management Science Society
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• v.28 no.4
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• pp.1-19
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• 2003

This paper studies power and rate control for data users on the forward link of CDMA system with two cells. The QoS for data users is specified by delay and error rate constraints as well as a family of utility functions representing system throughput and fairness among data users. Optimal power and rate allocation problem is mathematically formulated as a nonlinear programming problem, which is to maximize total utility under delay and error rate constraints, and optimal power and rate allocation scheme (OPRAS) is proposed to obtain a good solution in a fast time. Computational experiments show that the proposed scheme OPRAS works very well and increases total utility compared to the separate power and rate allocation scheme (SPARS) which considers each cell individually.

• Information and Communications Magazine
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• v.13 no.8
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• pp.103-122
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• 1996

초고속정보통신망의 구축이 효율적이고 신뢰성 있는 서비스를 제공하기 위하여 위성/지상망을 통합한 혼합망 구조로 개발됨에 따라 지상 광파이버를 기반으로 개발된 ATM 전송프로토콜을 위성망에 직접적으로 적용하기 위한 기술개발이 요구된다. 이러한 점을 고려하여 본 고에서는 위성 ATM(Asynchronous Transfer Mode) 전송에 따른 문제점 분석, 개선방안 및 성능평가를 수행하였다. 혼합망 구성에 따른 위성망의 구조를 접속된 지상노드의 유형 및 위성시스템 특성에 따라 3가지 유형으로 분류하여 제시하였고, 위성 ATM 전송에 따른 기술적인 문제점을 채널 BER과 위성지연 측면으로 분류하여 제시하였다. 위성채널 BER 성능개선을 위한 2가지 방안(인터리빙, HEC 보강)을 제시하였으며 위성지연분석은 고정지연(Fixed delay)과 셀지연변이(CDV : Cell Delay Variation) 측면에서 성능평가를 수행하였다.

• Proceedings of the IEEK Conference
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• 2002.06e
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• pp.79-82
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• 2002

In this paper, we proposed a multiplicative algorithm for two polynomials in existence coefficients over finite field GF(3$^{m}$ ). Using the proposed multiplicative algorithm, we constructed the multiplier of modular architecture with parallel in-output. The proposed multiplier is composed of (m+1)$^2$identical cells, each cell consists of single mod(3) additional gate and single mod(3) multiplicative gate. Proposed multiplier need single mod(3) multiplicative gate delay time and m mod(3) additional gate delay time not clock. Also, the proposed architecture is simple, regular and has the property of modularity, therefore well-suited for VLSI implementation.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.8
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• pp.33-41
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• 1998

We have designed a high speed and low power 16bit-ELM adder with variable-sized cells uitlizing the fact that the logic depth of lower bit position is less than that of the higher bit position int he conventional ELM architecture. As a result of HSPICE simulation with 0.8.mu.m single-poly double-metal LG CMOS process parameter, out 16bit-ELM adder with variable-sized cells shows the reduction of power-delay-product, which is less than that of the conventional 16bit-ELM adder with reference-sized cells by 19.3%. We optimized the desin with various logic styles including static CMOs, pass-transistor logic and Wang's XOR/XNOR gate. Maximum delay path of an ELM adder depends on the implementation method of S cells and their logic style.