• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.1
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• pp.53-60
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• 2004

This work describes a l0b 150 MSample/s CMOS pipelined A/D converter (ADC) based on advanced bootsuapping techniques for higher input bandwidth than a sampling rate. The proposed ADC adopts a typical multi-step pipelined architecture, employs the merged-capacitor switching technique which improves sampling rate and resolution reducing by $50\%$ the number of unit capacitors used in the multiplying digital-to-analog converter. On-chip current and voltage references for high-speed driving capability of R & C loads and on-chip decimator circuits for high-speed testability are implemented with on-chip decoupling capacitors. The proposed AU is fabricated in a 0.18 um 1P6M CMOS technology. The measured differential and integral nonlinearities are within $-0.56{\~}+0.69$ LSB and $-1.50{\~}+0.68$ LSB, respectively. The prototype ADC shows the signal-to-noise-and-distortion ratio (SNDR) of 52 dB at 150 MSample/s. The active chip area is 2.2 mm2 (= 1.4 mm ${\times}$ 1.6 mm) and the chip consumes 123 mW at 150 MSample/s.

• Journal of IKEEE
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• v.25 no.4
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• pp.591-597
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• 2021

This paper proposes an EMC-aware PCB design method to reduce electromagnetic emission, where trace length and teturn path of critical signal are shortened by changing chip location and trace layout on the PCB, while additional filters or decoupling capacitors are not required. In the proposed method, signal velocity is calculated for various signals on the PCB. Critical signal with the fastest signal velocity is determined and its return path is shortened as much as possible by placing chip location and trace routing first. Return path of critical signal should be carefully designed not to have discontinuity. Power plane and ground plane should be carefully designed not to be divided, since these planes are the reference of return path. The proposed method was applied to automotive directional Bluetooth speaker which failed to pass CISPR 32 and CISPR 25 EMC tests. Its PCB was redesigned based on the proposed method and it easily passed the EMC tests. The proposed method is useful to EMC-sensitive electronic equipments.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.2
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• pp.135-147
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• 2015

With the miniaturization and digitalization of electronics industry, demand for Multi-Layer Ceramic Capacitor(MLCC) has increased steadily because of its various applications such as DC Blocking, Decoupling and Filtering etc. The modeling techniques of MLCC has been studied for a long time but most of these modeling method can only be applied after measurement and this has some losses of material, time in both production stage and measurement stage. This paper proposes the modeling method which can predict the frequency characteristics of MLCC from structure data and material data in design stage. The impedance of N-Layer Capacitor can be expressed in differential mathematical form based on coupled transmission line equations. By using this formula, we can predict the impedance of MLCC. As a result, proposed modeling is correspond with simulation, and it takes much less time to obtain the result than the simulation.