• The Transactions of the Korean Institute of Electrical Engineers
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• v.40 no.4
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• pp.331-341
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• 1991

The discrete cosine transform (DCT) is widely used in many signal processing areas, including image and speech data compression. In this paper, we investigate a fixed-point error analysis for fast DCT algorithms, namely, Lee [6], Hou [7] and Vetterli [8]. A statistical model for fixed-point error is analyzed to predict the output noise due to the fixed-point implementation. This paper deals with two's complement fixed-point data representation with truncation and rounding. For a comparison purpose, we also investigate the direct form DCT algorithm. We also propose a suitable scaling model for the fixed-point implementation to avoid an overflow occurring in the addition operation. Computer simulation results reveal that there is a close agreement between the theoretical and the experimental results. The result shows that Vetterli's algorithm is better than the other algorithms in terms of SNR.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.1
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• pp.234-243
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• 1995

An arry circuit is designed for parallel computation of vector-radix 2-D discrete cosine transform (VR-FCT) which is a fast algorithm of DCT. By using a 2-D array of processing elements (PEs), the butterfly structure of the VR-FCT can be efficiently implemented with high condurrency and local communication geometry. The proposed implementation features architectural medularity, regularity and locality, so that it is very suitable for VLSI realization. Also, no transposition memory is required. The array core for (8$\times$8) 2-D DCT, which is designed usign ISRC 1.5.mu.m N-Well CMOS technology, consists of 64 PEs arranged in (8$\times$8) 2-D array and contains about 98,000 transistors on an area of 138mm$^{2}$. From simulation results, it is estimated that (8$\times$8) 2-D DCT can be computed in about 0.88 .mu.sec at 50 MHz clock frequency, resulting in the throughput rate of about 72${\times}10^[6}$ pixels per second.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.811-814
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• 2000

It this paper a VLSI architecture of the Shape-Adaptive Discrete Cosine Transform (SA-DCT) is described, which can be employed dedicatedly for MPEG-4 video codec. Adopting a fast DCT algorithm, the number of multipliers can be reduced by half in comparison with a conventional algorithm. This SA-DCT core with a small additional amount of hardware can perform the SA-Inverse DCT (SA-IDCT) by sharing multipliers and a transportation memory. The proposed SA-DCT core is integrated with 40,000 gates by using 0.35$mu$m triple-metal CMOS technology, which operates at 20 Mhz, and hence enables the realtime codec of CIF ($352{\times}288$ pixels) pictures.

• Journal of KIISE:Software and Applications
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• v.31 no.7
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• pp.901-910
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• 2004

In this paper, we propose a content-based MPEG transcoding method using a discontinuity feature in the Discrete Cosine Transform (DCT) domain. A DCT block is transcoded differently depending on the height of dominant discontinuity within a block. In the experiment, we show the result that the video quality of content-based transcoding is better than that of a constant cut-off method and the processing time of the adaptive method is much faster compared with the pixel domain methods in the same bandwidth.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.7A
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• pp.529-536
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• 2003

In this Paper, a new DCT HLMS DFE(Discrete Cosine Transform Hierarchical Least Mean Square Decision Feedback Equalizer) algorithm is proposed to improve the convergence speed and MSE(Mean Square Error) performance of a receive channel equalizer in ATSC(Advanced Television System Committee) 8VSB(Vestigial Side Band) digital terrestrial TV system. The proposed algorithm reduces the eigenvalue range of input data autocorrelation by transforming LMS (Least Mean Square) DFE into the subfilter of hierarchical structure. Moreover, the use of DCT and power estimation algorithm makes it possible to reduce the eigenvalue deviation of input data which results from distortion and delay of the receive signal in the miulti-path environment. Simulation results show that proposed DCT HLMS DFE has SNR improvement of approximately 3.8dB, 5dB and 2dB as compared to LMS DFE when the equalized symbol error rate is 0.2 in ATTC defined digital terrestrial TV broadcasting channels A, B and F, respectively.

• Proceedings of the KIEE Conference
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• 2008.04a
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• pp.91-92
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• 2008

본 논문에서는 기존의 H.264/AVC의 spatial 영역에서 Intra prediction 기법과 달리 H.264/AVC에서 사용하는 Integer DCT 영역에서 Intra prediction 기법을 제안한다. 이를 위하여 Integer DCT 영역에서 Intra prediction을 수행하는 모든 과정을 matrix multiplication으로 표현하여 Intra prediction을 수행하는 matrix를 유도한다. Intra prediction을 수행하는 matrix를 각 모드에 알맞게 설계하고, 이 matrix를 Integer DCT 영역에서 사용할 수 있도록 orthogonal한 Integer matrix를 설계한다. 실험을 통하여 제안한 Integer DCT 영역에서 Intra prediction 기법이 기존의 H.264/AVC의 spatial 영역에서 intra prediction 기법과 성능이 동일하면서 어떻게 matrix multiplication에 연산들을 포함시켜서 단순화 할 수 있는지를 보여주겠다. 또한 H.264/AVC에서 제공하는 intra prediction 각 모드에 대해 계산상 복잡도를 분석하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.9C
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• pp.879-885
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• 2002

The performance of communication systems should be tested against a set of requirements. To this end, noise generation systems are used to generate noise signals with specified characteristics. In this paper, we propose the area & power-efficient noise generation system based on DCT method. It is shown that the proposed structure results in area reduction of non-DCT block by 44∼47%. Moreover, since the proposed structure does not use high-speed internal clock, it achieves power reduction by 74∼77%.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1998.06a
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• pp.189-192
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• 1998

본 논문은 DCT (Discrete Cosine Transform) 영역에서의 압축 동영상 하향 전환기법 (down conversion)을 제안한다. DCT 영역에서의 하향 전환이 완전 복호화한 후 공간 영역에서 하향 전환하는 것보다 계산량 측면에서 상당한 이점이 있다. 또한 복호기 루프 내에서 영상 크기가 줄기 때문에 메모리의 부담을 덜 수 있다. 가장 간다한 방법으로서 복원된 영상의 화질이 약잔 떨어지더라도 계산량과 메모리를 줄이기 위해 8x8 DCT 블록의 저주파 영역의 4x4 DCT 계수만을 추출하여 4x4 IDCT하는 기법이 널리 알려져 있다. 본 논문에서는 변형된 4x4 IDCT 기저 함수를 이용한 새로운 DCT 영역에서의 하향 전환 기법을 제안한다. 모의실험을 통해 제안한 기법이 기존의 DCT 영역에서의 하향 전환기법과 같은 계산량 및 메모리로 향상된 PSNR을 갖는다는 것을 보인다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.10 s.113
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• pp.976-984
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• 2006

OFDM system is very useful for the high speed communication system. However, OFDM system has a serious problem of high PAPR that results from the so many subcarriers in the same phase. This OFDM signal is distorted through the nonlinear HPA(High Power Amplifier). Tone reservation method is to insert tone signal in several types to reduce the PAPR after iterating this process by changing the tone signal. Also discrete cosine transform(DCT) can reduces the PAPR as multiplying the cosine value to change the angle and mix up with the data. In the paper, the combination of the TR method and DCT method is newly proposed for more effective reduction of the PAPR. Simulation results show that the proposed method outperforms the conventional simple TR method and DCT method with respect to the PAPR reduction and BER performance.

• Journal of Broadcast Engineering
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• v.6 no.2
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• pp.121-130
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• 2001

We propose an efficient DCT-domain video transcoding algorithm for flexible for bit-rate video communications. Video transcoding provides communication fiexibility by adaptively changing the bit-rate of compressed bit stream. During the transcoding process, adrift error is unavoidable because of the difference between reference images in the series of encoding and decoding. For solving the drift error problem, cascade pixel-domain transcoder (CPDT) has been proposed. CPDT, however, requires highly complex hardware and heavy computational overhead. In this paper we propose a DCT-domain transcoding technique, which enables efficient transcoding without any drift error. The proposed cascade DCT-domain transcoder (CDDT) is realized by new motion compensation and down-sampling methods in the DCT-domain.