• 한국초전도학회:학술대회논문집
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• v.14
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• pp.71-71
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• 2004

• Progress in Superconductivity
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• v.6 no.2
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• pp.113-117
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• 2005

In this study, electromagnetic analysis of current paths including meander pattern, spiral pattern, and bi-spiral pattern were performed and in order to verity the analysis results, experiments tests including quench test, and insulation tests were performed. In addition, bubble corner concepts were introduced to enhance insulation reliability. From our study, bi-spiral pattern of YBCO thin films were rather effective for quench and insulation than the other patterns. So this current path pattern was adopted for YBCO thin films in order to develop 6.6 kV resistive fault current limiters. Finally YBCO thin films were connected in series and parallel to enhance capacity, and the test results of current limiting characteristics of 6.6kV resistive SFCL were successful. The Progress in Superconductivity is published every six month and serves as a channel for publications on superconductivity and related topics. The author(s) are required to submit THREE copies of the manuscripts along with original figures directly to the Editor.

• Korean Journal of Computational Design and Engineering
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• v.3 no.4
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• pp.223-235
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• 1998

A dedicated CAM(Computer-Aided Manufacturing) system has been developed, which generated tool-path to machine Styrofoam stamping die-patterns in Chrysler Corporation. A previous process to build die-patterns was to "stick build" the pattern, in which stock is cut & glued together, and then the NC machining of part-surface shape completes building a Styrofoam die-pattern. The current process utilizes the developed CAM system, and almost removes the manual work, consequently reduces the overall lead time. The paper presents the overall system structures, tool-path generation, and some features of Styrofoam pattern machining.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.2
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• pp.184-195
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• 1996

Beause BiCMOS logic circuits consist of CMOS part which constructs logic function and bipolar part which drives output load, the effect of short faults on BiCMOS logic circuits represented different types from that on CMOS. This paper proposes new test method which detects short faults on BiCMOS logic circuits using current path graph. Proposed method transforms BiCMOS circuits into raph constructed by nodes and edges using extended switch-level model and separates the transformed graph into pull-up part and pull-down part. Also, proposed method eliminates edge or add new edge, according ot short faults on terminals of transistor, and can detect short faults using current path graph that generated from on- or off-relations of transistor by input patterns. Properness of proposed method is verified by comparing it with results of spice simulation.

• Journal of Information Technology Services
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• v.17 no.4
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• pp.37-52
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• 2018

With the increasing severity of the shortage of highly-skilled IT personnel, more and more attention is being paid to the professional career path and systematic career management of IT employees. Although some studies have been conducted to describe the current status of IT personnel, limited attempts have been made to analyze the career paths or career patterns of IT professionals from a longitudinal perspective. In this context, this study explored the job career patterns of IT professionals in Korea and examined their relationship with subjective and objective career success. To identify job career patterns over time, detailed information about jobs and positions were used and an optimal matching analysis (OMA) was conducted to calculate the dissimilarity matrix between employees' career sequences, while a cluster analysis was used to categorize the meaningful groups based on this dissimilarity data. This analysis revealed that career patterns among Korean IT personnel are more varied than previously thought. These career types have a significant relationship with individual profiles, such as age, education, industry and company size, and account for significant variations in the three main career success variables, i.e. quality of life, assessment of software quality, and wage level. It is expected that the findings of this study will contribute to refining the Korean career path so as to retain IT personnel, and raise the need to improve the low quality of life and poor SW work environment of IT personnel.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.2
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• pp.97-105
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• 2016

Microcontrollers (MCUs) for endpoint smart sensor devices of internet-of-thing (IoT) are being implemented as system-on-chip (SoC) with on-chip instruction flash memory, in which user firmware is embedded. MCUs directly fetch binary code-based instructions through bit-line sense amplifier (S/A) integrated with on-chip flash memory. The S/A compares bit cell current with reference current to identify which data are programmed. The S/A in reading '0' (erased) cell data consumes a large sink current, which is greater than off-current for '1' (programmed) cell data. The main motivation of our approach is to reduce the number of accesses of erased cells by binary code level transformation. This paper proposes a built-in write/read path architecture using binary code inversion method based on hot-spot region detection of instruction code access to reduce sensing current in S/A. From the profiling result of instruction access patterns, hot-spot region of an original compiled binary code is conditionally inverted with the proposed bit-inversion techniques. The de-inversion hardware only consumes small logic current instead of analog sink current in S/A and it is integrated with the conventional S/A to restore original binary instructions. The proposed techniques are applied to the fully-custom designed MCU with ARM Cortex-M0$^{TM}$ using 0.18um Magnachip Flash-embedded CMOS process and the benefits in terms of power consumption reduction are evaluated for Dhrystone$^{TM}$ benchmark. The profiling environment of instruction code executions is implemented by extending commercial ARM KEIL$^{TM}$ MDK (MCU Development Kit) with our custom-designed access analyzer.

• Journal of Korean Port Research
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• v.13 no.2
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• pp.409-418
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• 1999

Gamcheon Bay has complicated and unique flow pattern which is affected by topography characteristics of a semi-closed bay and warm water discharge from the power plant located at the bay. It is very important to consider warm water discharge with tidal period and wind effects, which are mainly acting on the surface flow patterns in Gamcheon Bay. The results of observation show as follows; i) Because Gamcheon bay has much elongated shape to the north-south direction and narrow entrance with two separated breakwaters, the flow is very weak inside the bay. ii) The main flow path is at the west side of the bay. The direction of flood current is northward along the west side of the bay and the direction of ebb current is southward along the west side of the bay. The southward direction of warm water discharge has curved to the west side of the bay. iii)At the period of flood current for neap tide, the flow direction is southward in the bay, which is thought by the effects of warm water discharge. But at the bottom layer, the effects of tidal current reached to the middle of the bay, and showed features like eddy. iv) The wind effect is very strong, especially, prominent in the west and east side of the bay.

• Journal of KIISE:Databases
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• v.31 no.3
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• pp.320-330
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• 2004

Query languages for XML use paths in a data graph to represent queries. Actually, paths in a data graph are used as a basic constructor of an XML query. User can write more expressive Queries by using Patterns (e.g. regular expressions) for paths. There are many identical paths in a data graph because of the feature of semi-structured data. Current researches for indexing XML utilize identical paths in a data graph, but such an index can grow larger than source data graph and cannot guarantee efficient access path. In this paper we propose a partitioning technique that can partition all the paths in a data graph. We develop an index graph that can find appropriate partitions for a path query efficiently. The size of our index graph can be adjusted regardless of the source data. So, we can significantly improve the cost for index graph traversals. In the performance study, we show our index much faster than other graph based indexes.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.11
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• pp.730-742
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• 2014

In the case of On-demand routing protocol in cognitive radio ad-hoc networks, broadcasting of control packets may occur common control channel overload and packet collisions during the routing procedure. This situation is to increase the overhead of path finding and also limited to find the accurate and reliable path. Since reliable channel and path finding is restricted, path life time is shorten and path reliability is reduced. In this paper, we propose a new routing algorithm that reduces control channel overhead and increases path life time by considering the probability of appearance of primary user and channel status of neighbor nodes. Each node performs periodic local sensing to detect primary user signal and to derive primary user activity patterns. The probability of primary appearance on the current channel and the channel status can be obtained based on the periodic sensing. In addition, each node identifies the quality of the channel by message exchange through a common channel with neighbor nodes, then determines Link_Levels with neighbor nodes. In the proposed method, the Link Level condition reduces the number of control messages that are generated during the route discovery process. The proposed method can improve path life time by choosing a path through Path_Reliability in which stability and quality are weighted depending on the location. Through simulation, we show that our proposed algorithm reduces packet collisions and increases path life time in comparison with the traditional algorithm.

• Journal of Power Electronics
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• v.11 no.2
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• pp.173-178
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• 2011

In order to verify the performance of brushless DC (BLDC) motors, the simulation method has been widely used. The current of a BLDC motors flows on two phase windings to obtain a constant torque. However, the freewheeling current caused by the inductance component of a BLDC motor exists at the commutation point so that the current can flow on three phase windings at the same time. Due to the changes of the excited phases, the model equations are frequently changed during BLDC motor drive operation. The model equations can be also changed by the applied switching pattern since the current path in the inverter circuit changes according to switching pattern. A BLDC motor system can utilize various switching patterns for many different purposes. However, such changes of the model equations complicate the simulation procedure. In this paper, the technique to set up model equations is proposed to ease the simulation of a BLDC motor system through an inverter circuit analysis. The proposed technique will be verified using the C language. Although this method does not provide the level of detail obtainable from commercial simulation tools like PSIM or SIMULINK, it can provide an efficient way to quickly compare various conditions.