• 한국초전도학회:학술대회논문집
• /
• 한국초전도학회 2004년도 High Temperature Superconductivity Vol.XIV
• /
• pp.71-71
• /
• 2004

• Progress in Superconductivity
• /
• 제6권2호
• /
• pp.113-117
• /
• 2005

In this study, electromagnetic analysis of current paths including meander pattern, spiral pattern, and bi-spiral pattern were performed and in order to verity the analysis results, experiments tests including quench test, and insulation tests were performed. In addition, bubble corner concepts were introduced to enhance insulation reliability. From our study, bi-spiral pattern of YBCO thin films were rather effective for quench and insulation than the other patterns. So this current path pattern was adopted for YBCO thin films in order to develop 6.6 kV resistive fault current limiters. Finally YBCO thin films were connected in series and parallel to enhance capacity, and the test results of current limiting characteristics of 6.6kV resistive SFCL were successful. The Progress in Superconductivity is published every six month and serves as a channel for publications on superconductivity and related topics. The author(s) are required to submit THREE copies of the manuscripts along with original figures directly to the Editor.

• 한국CDE학회논문집
• /
• 제3권4호
• /
• pp.223-235
• /
• 1998

A dedicated CAM(Computer-Aided Manufacturing) system has been developed, which generated tool-path to machine Styrofoam stamping die-patterns in Chrysler Corporation. A previous process to build die-patterns was to "stick build" the pattern, in which stock is cut & glued together, and then the NC machining of part-surface shape completes building a Styrofoam die-pattern. The current process utilizes the developed CAM system, and almost removes the manual work, consequently reduces the overall lead time. The paper presents the overall system structures, tool-path generation, and some features of Styrofoam pattern machining.

• 전자공학회논문지A
• /
• 제33A권2호
• /
• pp.184-195
• /
• 1996

Beause BiCMOS logic circuits consist of CMOS part which constructs logic function and bipolar part which drives output load, the effect of short faults on BiCMOS logic circuits represented different types from that on CMOS. This paper proposes new test method which detects short faults on BiCMOS logic circuits using current path graph. Proposed method transforms BiCMOS circuits into raph constructed by nodes and edges using extended switch-level model and separates the transformed graph into pull-up part and pull-down part. Also, proposed method eliminates edge or add new edge, according ot short faults on terminals of transistor, and can detect short faults using current path graph that generated from on- or off-relations of transistor by input patterns. Properness of proposed method is verified by comparing it with results of spice simulation.

• 한국IT서비스학회지
• /
• 제17권4호
• /
• pp.37-52
• /
• 2018

With the increasing severity of the shortage of highly-skilled IT personnel, more and more attention is being paid to the professional career path and systematic career management of IT employees. Although some studies have been conducted to describe the current status of IT personnel, limited attempts have been made to analyze the career paths or career patterns of IT professionals from a longitudinal perspective. In this context, this study explored the job career patterns of IT professionals in Korea and examined their relationship with subjective and objective career success. To identify job career patterns over time, detailed information about jobs and positions were used and an optimal matching analysis (OMA) was conducted to calculate the dissimilarity matrix between employees' career sequences, while a cluster analysis was used to categorize the meaningful groups based on this dissimilarity data. This analysis revealed that career patterns among Korean IT personnel are more varied than previously thought. These career types have a significant relationship with individual profiles, such as age, education, industry and company size, and account for significant variations in the three main career success variables, i.e. quality of life, assessment of software quality, and wage level. It is expected that the findings of this study will contribute to refining the Korean career path so as to retain IT personnel, and raise the need to improve the low quality of life and poor SW work environment of IT personnel.

• 대한임베디드공학회논문지
• /
• 제11권2호
• /
• pp.97-105
• /
• 2016

Microcontrollers (MCUs) for endpoint smart sensor devices of internet-of-thing (IoT) are being implemented as system-on-chip (SoC) with on-chip instruction flash memory, in which user firmware is embedded. MCUs directly fetch binary code-based instructions through bit-line sense amplifier (S/A) integrated with on-chip flash memory. The S/A compares bit cell current with reference current to identify which data are programmed. The S/A in reading '0' (erased) cell data consumes a large sink current, which is greater than off-current for '1' (programmed) cell data. The main motivation of our approach is to reduce the number of accesses of erased cells by binary code level transformation. This paper proposes a built-in write/read path architecture using binary code inversion method based on hot-spot region detection of instruction code access to reduce sensing current in S/A. From the profiling result of instruction access patterns, hot-spot region of an original compiled binary code is conditionally inverted with the proposed bit-inversion techniques. The de-inversion hardware only consumes small logic current instead of analog sink current in S/A and it is integrated with the conventional S/A to restore original binary instructions. The proposed techniques are applied to the fully-custom designed MCU with ARM Cortex-M0$^{TM}$ using 0.18um Magnachip Flash-embedded CMOS process and the benefits in terms of power consumption reduction are evaluated for Dhrystone$^{TM}$ benchmark. The profiling environment of instruction code executions is implemented by extending commercial ARM KEIL$^{TM}$ MDK (MCU Development Kit) with our custom-designed access analyzer.

• 한국항만학회지
• /
• 제13권2호
• /
• pp.409-418
• /
• 1999

Gamcheon Bay has complicated and unique flow pattern which is affected by topography characteristics of a semi-closed bay and warm water discharge from the power plant located at the bay. It is very important to consider warm water discharge with tidal period and wind effects, which are mainly acting on the surface flow patterns in Gamcheon Bay. The results of observation show as follows; i) Because Gamcheon bay has much elongated shape to the north-south direction and narrow entrance with two separated breakwaters, the flow is very weak inside the bay. ii) The main flow path is at the west side of the bay. The direction of flood current is northward along the west side of the bay and the direction of ebb current is southward along the west side of the bay. The southward direction of warm water discharge has curved to the west side of the bay. iii)At the period of flood current for neap tide, the flow direction is southward in the bay, which is thought by the effects of warm water discharge. But at the bottom layer, the effects of tidal current reached to the middle of the bay, and showed features like eddy. iv) The wind effect is very strong, especially, prominent in the west and east side of the bay.

• 한국정보과학회논문지:데이타베이스
• /
• 제31권3호
• /
• pp.320-330
• /
• 2004

XML에 대한 질의 언어는 데이타 그래프 내의 경로를 이용하여 질의를 표현한다. 특히, 경로에 패턴 (예를 들어, 정규식)을 사용함으로써, 데이타의 구조를 정확히 알지 못하더라도 질의가 가능하도록 한다. 이때, 패턴을 이용하는 질의는 데이타 그래프의 탐색범위를 크게 넓히게 된다. 기존의 XML색인 기법은 질의의 탐색범위를 줄이기 위해 데이타 그래프 내의 서로 동일한 경로들을 하나로 묶어 작은 크기의 색인 그래프를 생성하는 방법을 이용한다. 하지만 이러한 색인들은 많은 경우 색인의 크기가 데이터 그래프의 크기만큼 증가하게 되어 질의의 탐색범위를 줄이지 못하고, 따라서 효율적인 질의 처리를 보장하지 못한다. 본 논문에서는 데이타 내에 존재하는 모든 경로를 분할(partitioning)하고 질의 처리 시 질의에 맞는 분할 영역을 빠르게 찾아낼 수 있는 색인 그래프를 제안한다. 본 논문에서 제안하는 색인 그래프는 데이터 그래프의 크기와 상관없이 색인 그래프의 크기를 조절할 수 있다. 따라서 색인 그래프의 크기를 작게 구성함으로써 색인 그래프 탐색 비용을 크게 줄일 수 있다. 본 논문에서는, 실험을 통해 기존의 그래프 기반색인 기법들보다 본 논문의 색인 기법이 보다 효율적임을 보이고 색인의 크기 변화에 따른 성능 변화에 대해 알아본다.

• 한국통신학회논문지
• /
• 제39B권11호
• /
• pp.730-742
• /
• 2014

인지무선 애드혹 네트워크(Cognitive Radio Ad-hoc Networks)에서 요구기반 라우팅을 수행할 경우, 경로 탐색 과정에서 발생하는 경로탐색 메시지의 브로드캐스팅은 공통 제어 채널의 과부하를 유발하고 패킷 간의 충돌을 발생시킨다. 이런 현상은 경로탐색의 오버헤드를 증가 시키며, 정확하고 신뢰성있는 경로의 탐색에 제한을 받게 된다. 이로 인하여 신뢰성있는 채널을 찾는 경로가 제한되기 때문에 경로의 생존 시간이 단축되고 경로의 안정성이 감소된다. 본 논문에서는 인지무선 ad-hoc네트워크에서 주사용자의 출현 가능성과 주변 사용자의 상황을 고려하여 패킷 충돌을 감소시키고 경로의 생존시간을 향상 시키는 라우팅 알고리즘을 제안한다. 각 노드는 주기적인 센싱을 통해 주사용자의 사용패턴을 감지하고 채널의 사용 확률과 현재 채널 상태를 알고 있다. 또한 이웃 노드와 메시지 교환을 통해 공통된 채널과 해당 채널의 품질을 파악하여 노드 사이에 링크 레벨을 부여한다. 제안된 방법에서는 링크 레벨을 이용하여 경로 탐색 과정에서 발생하는 제어 메시지의 수를 감소시킨다. 또한 링크의 생존성과 품질을 홉 카운트에 따라 가중치를 부여하여 경로를 선택함으로써 경로의 생존 시간을 향상 시킬 수 있다. 성능 평가를 통해 기존의 방법 보다 제안된 방법을 이용하여 라우팅을 수행할 경우 제어 채널의 오버헤드가 감소되고 경로의 생존시간이 증가하는 것을 확인 할 수 있다.

• Journal of Power Electronics
• /
• 제11권2호
• /
• pp.173-178
• /
• 2011

In order to verify the performance of brushless DC (BLDC) motors, the simulation method has been widely used. The current of a BLDC motors flows on two phase windings to obtain a constant torque. However, the freewheeling current caused by the inductance component of a BLDC motor exists at the commutation point so that the current can flow on three phase windings at the same time. Due to the changes of the excited phases, the model equations are frequently changed during BLDC motor drive operation. The model equations can be also changed by the applied switching pattern since the current path in the inverter circuit changes according to switching pattern. A BLDC motor system can utilize various switching patterns for many different purposes. However, such changes of the model equations complicate the simulation procedure. In this paper, the technique to set up model equations is proposed to ease the simulation of a BLDC motor system through an inverter circuit analysis. The proposed technique will be verified using the C language. Although this method does not provide the level of detail obtainable from commercial simulation tools like PSIM or SIMULINK, it can provide an efficient way to quickly compare various conditions.