• Title/Summary/Keyword: crypto co-processor

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A Software Implementation of The Elliptic Curve Digital Signature Algorithm on a Embedded System (임베디드 시스템에서의 ECDSA(Elliptic Curve Digital Signature Algorithm) 구현)

  • Kim, Hyeon-Ik;Kim, Yong-Min;Jeong, Seok-Won;Lee, Sang-Jin;Jeong, Chang-Hun
    • Proceedings of the KIEE Conference
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    • 2003.11c
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    • pp.1014-1017
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    • 2003
  • In this paper, after the crypto acceleration board of the server-termination type is designed, we implement the Elliptic Curve Digital Signature Algorithm on the board that serves data integrity and user authentication. For implementing ECDSA, we use crypto co-processor, MPC180, to reduce the computation burden of main Processor (MPC860) on the board. By using crypto co-processor, the computation efficiency in case prime field is improved more between 90 and 100 times than the software library and between 20 and 90 times in case binary field. Our result is expect to apply for SSL acceleration board.

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A Design of Security SoC Prototype Based on Cortex-M0 (Cortex-M0 기반의 보안 SoC 프로토타입 설계)

  • Choi, Jun-baek;Choe, Jun-yeong;Shin, Kyung-wook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2019.05a
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    • pp.251-253
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    • 2019
  • This paper describes an implementation of a security SoC (System-on-Chip) prototype that interfaces a microprocessor with a block cipher crypto-core. The Cortex-M0 was used as a microprocessor, and a crypto-core implemented by integrating ARIA and AES into a single hardware was used as an intellectual property (IP). The integrated ARIA-AES crypto-core supports five modes of operation including ECB, CBC, CFB, CTR and OFB, and two master key sizes of 128-bit and 256-bit. The integrated ARIA-AES crypto-core was interfaced to work with the AHB-light bus protocol of Cortex-M0, and the crypto-core IP was expected to operate at clock frequencies up to 50 MHz. The security SoC prototype was verified by BFM simulation, and then hardware-software co-verification was carried out with FPGA implementation.

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A study on high performance Java virtual machine for smart card (스마트카드용 고성능 자바가상기계에 대한 연구)

  • Jung, Min-Soo
    • Journal of the Korean Data and Information Science Society
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    • v.20 no.1
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    • pp.125-137
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    • 2009
  • Smart card has a small sized micro computer chip. This chip contains processor, RAM, ROM, clock, bus system and crypto-co-processor. Hence it is more expensive, complicated and secure chip compared with RFID tag. The main application area of smart card is e-banking and secure communications. There are two kinds of smart card platforms; open platform and closed one. Java card is the most popular open platform because of its security, platform independency, fast developing cycle. However, the speed of Java card is slower than other ones, hence there have been hot research topics to improve the performance of Java card. In this paper, we propose an efficient transaction buffer management to improve the performance of Java card. The experimental result shows the advantage of our method.

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A Hardware Implementation of the Underlying Field Arithmetic Processor based on Optimized Unit Operation Components for Elliptic Curve Cryptosystems (타원곡선을 암호시스템에 사용되는 최적단위 연산항을 기반으로 한 기저체 연산기의 하드웨어 구현)

  • Jo, Seong-Je;Kwon, Yong-Jin
    • Journal of KIISE:Computing Practices and Letters
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    • v.8 no.1
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    • pp.88-95
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    • 2002
  • In recent years, the security of hardware and software systems is one of the most essential factor of our safe network community. As elliptic Curve Cryptosystems proposed by N. Koblitz and V. Miller independently in 1985, require fewer bits for the same security as the existing cryptosystems, for example RSA, there is a net reduction in cost size, and time. In this thesis, we propose an efficient hardware architecture of underlying field arithmetic processor for Elliptic Curve Cryptosystems, and a very useful method for implementing the architecture, especially multiplicative inverse operator over GF$GF (2^m)$ onto FPGA and futhermore VLSI, where the method is based on optimized unit operation components. We optimize the arithmetic processor for speed so that it has a resonable number of gates to implement. The proposed architecture could be applied to any finite field $F_{2m}$. According to the simulation result, though the number of gates are increased by a factor of 8.8, the multiplication speed We optimize the arithmetic processor for speed so that it has a resonable number of gates to implement. The proposed architecture could be applied to any finite field $F_{2m}$. According to the simulation result, though the number of gates are increased by a factor of 8.8, the multiplication speed and inversion speed has been improved 150 times, 480 times respectively compared with the thesis presented by Sarwono Sutikno et al. [7]. The designed underlying arithmetic processor can be also applied for implementing other crypto-processor and various finite field applications.