• 한국콘텐츠학회논문지
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• 제17권3호
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• pp.329-336
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• 2017

비디오 압축에서 움직임 추정 기법은 영상 화질과 발생 비트량에 있어서 중요한 역할을 하지만 많은 계산 복잡도를 요구한다. 다수의 카메라로 촬영한 동영상인 다시점 비디오는 카메라의 수에 비례하여 데이터의 양이 기하급수적으로 증가하기 때문에 움직임 추정에 많은 계산량을 필요하다. 본 논문에서 다시점 비디오의 부호화를 위한 움직임 추정의 계산량을 줄이면서 화질과 비트량을 유지하는 움직임 추정 기법을 제안한다. 제안한 움직임 추정 기법은 움직임 벡터들의 분포 특성과 영상 블록들의 움직임 특성을 이용한다. 제안한 움직임 추정기법은 계층적 움직임 추정 기법으로 대칭형 멀티 마름모 패턴, 대각선 패턴, 사각형 패턴 그리고 정교한 패턴으로 구성되어 있다. 제안한 움직임 추정 기법은 움직임 벡터들과 블록 움직임의 특성들을 이용하여 패턴들의 탐색 점들을 탐색 영역 내에 대칭적으로 배치하고 블록 움직임 크기에 따라 적응적으로 탐색 패턴을 선택하여 움직임 벡터를 추정한다. 제안한 기법의 성능은 JMVC의 고속 움직임 추정 기법인 TZ 탐색 기법과 전역 탐색 기법인 PBS (Pel Block Search)의 성능과 비교한 경우, 영상 화질면에서와 발생 비트량면에서 비슷하지만 움직임 추정에 필요한 계산량을 각각 약 40~75%, 98%감소시킨다.

• 한국콘텐츠학회논문지
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• 제18권12호
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• pp.35-45
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• 2018

움직임 추정은 동영상 내에 존재하는 중복된 데이터를 제거하기 때문에 영상 압축에서 중요한 역할을 하지만 많은 계산량을 요구하므로 계산량을 줄이기 위한 많은 고속 움직임 추정 기법이 제안되어 왔다. 다시점 비디오는 하나의 3차원 영상을 여러 시점에서 다수의 카메라로 촬영한 영상으로 다시점 비디오의 계산량은 카메라 수에 비례하여 증가한다. 따라서 다시점 비디오를 효율적으로 부호화하기 위한 움직임 추정 기법이 필요하다. 본 논문에서는 블록의 시공간적 상관성과 블록의 움직임 특성에 따라 적응적으로 탐색 패턴을 선택하여 움직임 벡터를 추정하는 움직임 추정 기법을 제안한다. 실험 결과, 제안한 움직임 추정 기법의 성능을 JMVC(Joint Multi-view Video Coding)의 TZ탐색과 전역탐색 기법의 성능과 비교한 경우, 영상 화질과 발생된 비트량을 비슷하지만 움직임 추정에 필요한 계산량은 각각 약 70~75%, 99%를 줄인다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
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• pp.1181-1184
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• 1987

The input-output relation for nonlinear systems can be explicitly represented by the Volterra functional series and it is characterized by the Volterra kernels. A block diagram reduction method is proposed to determine the Volterra kernels and is compared with the direct substitution technique. The former method can significantly reduce the computational complexity.

• 한국컴퓨터정보학회논문지
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• 제21권4호
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• pp.25-30
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• 2016

We consider energy efficient transmit and receive strategy for a delay sensitive data. More specifically, we investigate an energy optimum scheduling characteristics for the 2 user interference channel where each user interferes to each other. First, we determine the optimum transmission rate region each individual user may have for optimum transmission. Next, we consider the optimum transmission region of two users together. Shortest path algorithm can be used for further reduction of search space. Eventually, we can reduce computational complexity. We then examine the performance of the optimum transmission strategy for various system environments.

• 대한전자공학회논문지
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• 제25권3호
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• pp.315-321
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• 1988

The input-output relation for nonlinear systems can e explicitly represented by the volterra functional series and it is characterized by the Volterra kernels. A block diagram reduction method is proposed to determine the Volterra kernels for nonlinear differential equations and is compared with the direct substitution techniques. The former method can significantly reduce the computational complexity. A degree of nonlinearity is defined and analyzed for the analysis of nonlinear systems.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(4)
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• pp.123-126
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• 2001

Block filter implementation technique for uniform filter banks is uniform in this paper. By applying block filter into decimation and interpolation filters, it is shown that down and up samplers are cancelled out in respective liters. Furthermore by applying block filters into uniform filter banks, significant reduction for computational complexity is achieved since prototype filter can be shared in each channel implementation. Also, it is shown that proposed implementation is a reconfigurable structure in terms of order variation.

• ETRI Journal
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• 제32권4호
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• pp.596-602
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• 2010

This paper proposes a computationally efficient learning-based super-resolution algorithm using k-means clustering. Conventional learning-based super-resolution requires a huge dictionary for reliable performance, which brings about a tremendous memory cost as well as a burdensome matching computation. In order to overcome this problem, the proposed algorithm significantly reduces the size of the trained dictionary by properly clustering similar patches at the learning phase. Experimental results show that the proposed algorithm provides superior visual quality to the conventional algorithms, while needing much less computational complexity.

• 한국통신학회논문지
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• 제25권9B호
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• pp.1604-1608
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• 2000

The three-step search (TSS) algorithm for block motion estimation has been widely used in real-time video coding due to the simplicity of the algorithm significant reduction of computationl cost and good performance. In this paper an improved three-step search (ITS) algorithm is proposed to improve the performance of the TSS algorithm. Simulation results show that in terms of motion compensation errors the proposed ITSS outperforms some popular fast search algorithms while it has the lower computational complexity.

• 대한원격탐사학회지
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• 제7권1호
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• pp.13-27
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• 1991

DEM(digital elevation map) is a very useful information in various applications. In this paper, we have studied on the terrain matching algorithm using the DEM, which was proposed by Rodriguez and Aggarwal(1990) for an aircraft navigation system. We evaluated its performance using syntactic images. Cliff maps and critical points are used for the reduction of computation time and information size to be processed. The computer simulation shows that though the computational complexity is high, the technique is efficient even to noisy images.

• Journal of Communications and Networks
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• 제13권5호
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• pp.481-493
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• 2011

Multiple-input multiple-output (MIMO) technology provides high data rate and enhanced quality of service for wireless communications. Since the benefits from MIMO result in a heavy computational load in detectors, the design of low-complexity suboptimum receivers is currently an active area of research. Lattice-reduction-aided detection (LRAD) has been shown to be an effective low-complexity method with near-maximum-likelihood performance. In this paper, we advocate the use of systolic array architectures for MIMO receivers, and in particular we exhibit one of them based on LRAD. The "Lenstra-Lenstra-Lov$\acute{a}$sz (LLL) lattice reduction algorithm" and the ensuing linear detections or successive spatial-interference cancellations can be located in the same array, which is considerably hardware-efficient. Since the conventional form of the LLL algorithm is not immediately suitable for parallel processing, two modified LLL algorithms are considered here for the systolic array. LLL algorithm with full-size reduction-LLL is one of the versions more suitable for parallel processing. Another variant is the all-swap lattice-reduction (ASLR) algorithm for complex-valued lattices, which processes all lattice basis vectors simultaneously within one iteration. Our novel systolic array can operate both algorithms with different external logic controls. In order to simplify the systolic array design, we replace the Lov$\acute{a}$sz condition in the definition of LLL-reduced lattice with the looser Siegel condition. Simulation results show that for LR-aided linear detections, the bit-error-rate performance is still maintained with this relaxation. Comparisons between the two algorithms in terms of bit-error-rate performance, and average field-programmable gate array processing time in the systolic array are made, which shows that ASLR is a better choice for a systolic architecture, especially for systems with a large number of antennas.