• 제목/요약/키워드: complexity reduction algorithm

검색결과 266건 처리시간 0.027초

Systolic Arrays for Lattice-Reduction-Aided MIMO Detection

  • Wang, Ni-Chun;Biglieri, Ezio;Yao, Kung
    • Journal of Communications and Networks
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    • 제13권5호
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    • pp.481-493
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    • 2011
  • Multiple-input multiple-output (MIMO) technology provides high data rate and enhanced quality of service for wireless communications. Since the benefits from MIMO result in a heavy computational load in detectors, the design of low-complexity suboptimum receivers is currently an active area of research. Lattice-reduction-aided detection (LRAD) has been shown to be an effective low-complexity method with near-maximum-likelihood performance. In this paper, we advocate the use of systolic array architectures for MIMO receivers, and in particular we exhibit one of them based on LRAD. The "Lenstra-Lenstra-Lov$\acute{a}$sz (LLL) lattice reduction algorithm" and the ensuing linear detections or successive spatial-interference cancellations can be located in the same array, which is considerably hardware-efficient. Since the conventional form of the LLL algorithm is not immediately suitable for parallel processing, two modified LLL algorithms are considered here for the systolic array. LLL algorithm with full-size reduction-LLL is one of the versions more suitable for parallel processing. Another variant is the all-swap lattice-reduction (ASLR) algorithm for complex-valued lattices, which processes all lattice basis vectors simultaneously within one iteration. Our novel systolic array can operate both algorithms with different external logic controls. In order to simplify the systolic array design, we replace the Lov$\acute{a}$sz condition in the definition of LLL-reduced lattice with the looser Siegel condition. Simulation results show that for LR-aided linear detections, the bit-error-rate performance is still maintained with this relaxation. Comparisons between the two algorithms in terms of bit-error-rate performance, and average field-programmable gate array processing time in the systolic array are made, which shows that ASLR is a better choice for a systolic architecture, especially for systems with a large number of antennas.

고 복잡도 H.264/AVC의 실시간 압축을 위한 고속 인터 예측 부호화 기법 (A Fast Inter Prediction Encoding Algorithm for Real-time Compression of H.264/AVC with High Complexity)

  • 김영현;최현준;서영호;김동욱
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2006년도 하계종합학술대회
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    • pp.411-412
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    • 2006
  • In this paper, we proposed a fast algorithm for inter prediction included the most complexity in H.264/AVC. It decide search range according to direction of predicted motion vector, and then perform adaptive candidate spiral search. Simultaneously, it perform motion estimation of variable loop with threshold for variable block size. Conclusively, it is implemented in JM FME with high complexity applying to rate-distortion optimization. Experimental results show that significant complexity reduction is achieved while the degradation in video quality is negligible.

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PAPR reduction of OFDM systems using H-SLM method with a multiplierless IFFT/FFT technique

  • Sivadas, Namitha A.
    • ETRI Journal
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    • 제44권3호
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    • pp.379-388
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    • 2022
  • This study proposes a novel low-complexity algorithm for computing inverse fast Fourier transform (IFFT)/fast Fourier transform (FFT) operations in binary phase shift keying-modulated orthogonal frequency division multiplexing (OFDM) communication systems without requiring any twiddle factor multiplications. The peak-to-average power ratio (PAPR) reduction capacity of an efficient PAPR reduction technique, that is, H-SLM method, is evaluated using the proposed IFFT algorithm without any complex multiplications, and the impact of oversampling factor for the accurate calculation of PAPR is analyzed. The power spectral density of an OFDM signal generated using the proposed multiplierless IFFT algorithm is also examined. Moreover, the bit-error-rate performance of the H-SLM technique with the proposed IFFT/FFT algorithm is compared with the classical methods. Simulation results show that the proposed IFFT/FFT algorithm used in the H-SLM method requires no complex multiplications, thereby minimizing power consumption as well as the area of IFFT/FFT processors used in OFDM communication systems.

비지역적 평균 필터 기반의 개선된 커널 함수를 이용한 가우시안 잡음 제거 기법 (Gaussian Noise Reduction Technique using Improved Kernel Function based on Non-Local Means Filter)

  • 임월기;최현호;정제창
    • 한국방송∙미디어공학회:학술대회논문집
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    • 한국방송∙미디어공학회 2018년도 추계학술대회
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    • pp.73-76
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    • 2018
  • A Gaussian noise is caused by surrounding environment or channel interference when transmitting image. The noise reduces not only image quality degradation but also high-level image processing performance. The Non-Local Means (NLM) filter finds similarity in the neighboring sets of pixels to remove noise and assigns weights according to similarity. The weighted average is calculated based on the weight. The NLM filter method shows low noise cancellation performance and high complexity in the process of finding the similarity using weight allocation and neighbor set. In order to solve these problems, we propose an algorithm that shows an excellent noise reduction performance by using Summed Square Image (SSI) to reduce the complexity and applying the weighting function based on a cosine Gaussian kernel function. Experimental results demonstrate the effectiveness of the proposed algorithm.

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FPGA Implementation of SC-FDE Timing Synchronization Algorithm

  • Ji, Suyuan;Chen, Chao;Zhang, Yu
    • Journal of Information Processing Systems
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    • 제15권4호
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    • pp.890-903
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    • 2019
  • The single carrier frequency domain equalization (SC-FDE) technology is an important part of the broadband wireless access communication system, which can effectively combat the frequency selective fading in the wireless channel. In SC-FDE communication system, the accuracy of timing synchronization directly affects the performance of the SC-FDE system. In this paper, on the basis of Schmidl timing synchronization algorithm a timing synchronization algorithm suitable for FPGA (field programmable gate array) implementation is proposed. In the FPGA implementation of the timing synchronization algorithm, the sliding window accumulation, quantization processing and amplitude reduction techniques are adopted to reduce the complexity in the implementation of FPGA. The simulation results show that the algorithm can effectively realize the timing synchronization function under the condition of reducing computational complexity and hardware overhead.

유전자 알고리즘을 적용한 PTS에 의한 새로운 OFDM 시스템 PAR 감소 기법 (A New PAR Reduction Scheme in OFDM Systems by PTS Using Genetic Algorithm)

  • 김성수;김명제
    • 한국전자파학회논문지
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    • 제16권10호
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    • pp.995-1002
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    • 2005
  • Orthogonal frequency division multiplexing(OFDM) 시스템은 peak-to-average power ratio(PAR) 문제를 가진다. 일반적으로, partial transmit sequence(PTS) 기법을 이용하여 최적의 PAR 감소 성능을 얻기 위해서는 나눈 부블록의 수와 위상 요소(phase factor)에 관한 모든 탐색을 해야 한다 나눈 부블록 수와 위상 요소 수가 많을수록 PAR 감소 성능은 더 개선되지만, 계산량 또한 부블록 수에 따라 지수적으로 증가하여 송신기의 복잡도와 처리시간지연을 초래한다. 따라서 전송되는 신호의 PAR을 최적에 가깝게 줄이면서 동시에 계산량도 함께 줄일 수 있는 기법이 요구된다. 본 논문에서는 PTS 기법에서 최적의 PAR 감소 성능을 갖는 위상 요소를 찾기 위해 최적화 문제에 많이 사용되고 있는 유전자 알고리즘(Genetic Algerian: GA)을 이용함으로써 PAR 문제를 해결하고, 동시에 계산량도 함께 감소시켜 송신기의 복잡도와 처리시간 지연을 줄이는 기법을 제안하며, 제안된 기법의 PAR 감소 성능과 계산량을 기존의 제안된 방법들과 비교하였다. 또한, 본 논문에서 제안한 기법이 적은 계산량으로도 일반기법에 더 가까운 PAR 감소 성능을 가짐을 보였다.

Complexity-Reduced Algorithms for LDPC Decoder for DVB-S2 Systems

  • Choi, Eun-A;Jung, Ji-Won;Kim, Nae-Soo;Oh, Deock-Gil
    • ETRI Journal
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    • 제27권5호
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    • pp.639-642
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    • 2005
  • This paper proposes two kinds of complexity-reduced algorithms for a low density parity check (LDPC) decoder. First, sequential decoding using a partial group is proposed. It has the same hardware complexity and requires a fewer number of iterations with little performance loss. The amount of performance loss can be determined by the designer, based on a tradeoff with the desired reduction in complexity. Second, an early detection method for reducing the computational complexity is proposed. Using a confidence criterion, some bit nodes and check node edges are detected early on during decoding. Once the edges are detected, no further iteration is required; thus early detection reduces the computational complexity.

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Efficiency Improvement of the Fixed-Complexity Sphere Decoder

  • Mohaisen, Manar;Chang, Kyung-Hi
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • 제5권3호
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    • pp.494-507
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    • 2011
  • In this paper, we propose two schemes to reduce the complexity of fixed-complexity sphere decoder (FSD) algorithm in the ordering and tree-search stages, respectively, while achieving quasi-ML performance. In the ordering stage, we propose a QR-decomposition-based FSD signal ordering based on the zero-forcing criterion (FSD-ZF-SQRD) that requires only a few number of additional complex flops compared to the unsorted QRD. Also, the proposed ordering algorithm is extended using the minimum mean square error (MMSE) criterion to achieve better performance. In the tree-search stage, we introduce a threshold-based complexity reduction approach for the FSD depending on the reliability of the signal with the largest noise amplification. Numerical results show that in 8 ${\times}$ 8 MIMO system, the proposed FSD-ZF-SQRD and FSD-MMSE-SQRD only require 19.5% and 26.3% of the computational efforts required by Hassibi's scheme, respectively. Moreover, a third threshold vector is outlined which can be used for high order modulation schemes. In 4 ${\times}$ 4 MIMO system using 16-QAM and 64-QAM, simulation results show that when the proposed threshold-based approach is employed, FSD requires only 62.86% and 53.67% of its full complexity, respectively.

Efficiency Improvement of the Fixed-complexity Sphere Decoder

  • Mohaisen, Manar;Chang, Kyung-Hi
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • 제5권2호
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    • pp.330-343
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    • 2011
  • In this paper, we propose two schemes to reduce the complexity of fixed-complexity sphere decoder (FSD) algorithm in the ordering and tree-search stages, respectively, while achieving quasi-ML performance. In the ordering stage, we propose a QR-decomposition-based FSD signal ordering based on the zero-forcing criterion (FSD-ZF-SQRD) that requires only a few number of additional complex flops compared to the unsorted QRD. Also, the proposed ordering algorithm is extended using the minimum mean square error (MMSE) criterion to achieve better performance. In the tree-search stage, we introduce a threshold-based complexity reduction approach for the FSD depending on the reliability of the signal with the largest noise amplification. Numerical results show that in $8{\times}8$ MIMO system, the proposed FSD-ZF-SQRD and FSD-MMSE-SQRD only require 19.5% and 26.3% of the computational efforts required by Hassibi’s scheme, respectively. Moreover, a third threshold vector is outlined which can be used for high order modulation schemes. In $4{\times}4$ MIMO system using 16-QAM and 64-QAM, simulation results show that when the proposed threshold-based approach is employed, FSD requires only 62.86% and 53.67% of its full complexity, respectively.

Computationally efficient variational Bayesian method for PAPR reduction in multiuser MIMO-OFDM systems

  • Singh, Davinder;Sarin, Rakesh Kumar
    • ETRI Journal
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    • 제41권3호
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    • pp.298-307
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    • 2019
  • This paper investigates the use of the inverse-free sparse Bayesian learning (SBL) approach for peak-to-average power ratio (PAPR) reduction in orthogonal frequency-division multiplexing (OFDM)-based multiuser massive multiple-input multiple-output (MIMO) systems. The Bayesian inference method employs a truncated Gaussian mixture prior for the sought-after low-PAPR signal. To learn the prior signal, associated hyperparameters and underlying statistical parameters, we use the variational expectation-maximization (EM) iterative algorithm. The matrix inversion involved in the expectation step (E-step) is averted by invoking a relaxed evidence lower bound (relaxed-ELBO). The resulting inverse-free SBL algorithm has a much lower complexity than the standard SBL algorithm. Numerical experiments confirm the substantial improvement over existing methods in terms of PAPR reduction for different MIMO configurations.