• Title/Summary/Keyword: communication circuits

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A Study on the Electrical Characteristics of Track Circuits (궤도회로의 전기적 특성에 관한 연구)

  • Han, Seung-Jin;Chung, Young-Woon;Cheon, Ki-Ha;Lee, Key-Seo;Park, Young-Soo;You, Kwang-Kyun
    • Proceedings of the KIEE Conference
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    • 1996.07a
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    • pp.635-637
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    • 1996
  • Track circuit decides whether the section is occupied by train or free using the electrical characteristics of the rail, and sends information to the train using the rail as the medium of communication. So the electrical parameters of the rail are important to the track circuits. But they are influenced by the frequency of the transmitted signal and the environments like rain, snow and location of the rail. In this paper, the parameters of the rail is practically measured using the measurement method based on the 2-port network. The measurement demonstrates that the parameters of the rail is dependent on the frequency of the signal flowing on the rail and the environments like wheather. So this analysis of the parameters helps the design of track circuits.

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Design of 32-bit Carry Lookahead Adder Using ENMODL (ENMODL을 이용한 32 비트 CLA 설계)

  • 김강철;이효상;송근호;서정훈;한석붕
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.3 no.4
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    • pp.787-794
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    • 1999
  • This paper presents an ENMODL(enhances NORA MODL) circuit and implements a high-speed 32 bit CLA(carry lookahead adder) with the new dynamic logics. The proposed logic can reduce the area and the Propagation delay of carry because output inverters and a clocking PMOS of second stage can be omitted in two-stage MODL(multiple output domino logic) circuits. The 32-bit CLA is implemented with 0.8um double metal CMOS Process and the carry propagation delay of the adder is about 3.9 nS. The ENMODL circuits can improve the performance in the high-speed computing circuits depending on the degree of recurrence.

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Electromagnetic Interference Analysis of an Inhomogeneous Electromagnetic Bandgap Power Bus for High-Speed Circuits

  • Cho, Jonghyun;Kim, Myunghoi
    • Journal of information and communication convergence engineering
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    • v.15 no.4
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    • pp.237-243
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    • 2017
  • This paper presents an analysis of the electromagnetic interference of a heterogeneous power bus where electromagnetic bandgap (EBG) cells are irregularly arranged. To mitigate electrical-noise coupling between high-speed circuits, the EBG structure is placed between parallel plate waveguide (PPW)-based power buses on which the noise source and victim circuits are mounted. We examine a noise suppression characteristic of the heterogeneous power bus in terms of scattering parameters. The characteristics of the dispersion and scattering parameters are compared in the sensitivity analysis of the EBG structure. Electric field distributions at significant frequencies are thoroughly examined using electromagnetic simulation based on a finite element method (FEM). The noise suppression characteristics of the heterogeneous power bus are demonstrated experimentally. The heterogeneous power bus achieves significant reduction of electrical-noise coupling compared to the homogeneous power buses that are adopted in conventional high-speed circuit design. In addition, the measurements show good agreement with the FEM simulation results.

Estimation of Equivalent Circuit Parameters for Dual Resonance Electroacoustic Transducer Using Iterative Levy Method (두 개의 공진점을 갖는 광대역 초음파 전기음향 변환기의 등가회로변수 추정)

  • Lim, Jun-Seok;Pyeon, Yong-Guk
    • 전자공학회논문지 IE
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    • v.49 no.2
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    • pp.18-23
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    • 2012
  • A method to determine the equivalent circuits of broadband ultrasound transducers is necessary for designing filters that match the impedances of the transducer and the analysis of the transducer. A method is proposed to determine the equivalent circuits of broadband transducers with 2 resonances in the frequency band of interest. The circuit parameters are estimated by iterative Levy method with the measured electrical conductance data. The method is illustrated by computing the conductance and susceptance of the equivalent circuits of 3 types of broadband transducers. The equivalent circuit of a transducer.

Design of A Driving Circuit for Plasma Display Panels (플라즈마 디스플레이 패널 구동회로의 설계)

  • Choi, Ill-Hoon;Kim, Jun-Hyung;Lim, Beong-Ha;Yu, Sang-Dae
    • Proceedings of the KIEE Conference
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    • 2002.11c
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    • pp.554-557
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    • 2002
  • In this paper, PDP driving circuit is designed to show the pattern of still-image with ADS (Address Display Separation) driving method. The designed circuits consist of three stages which are the image processing program, digital logic parts, and power circuits. The Image processing program is designed serial-communication with RS-232C using BASIC language. Digital logic parts design ADS driving signals with Xilinx FPGA and are simulated by ModelSim 5.5f. Power circuits convert output of digital logic parts into high voltage which panel is drived.

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Analysis of Transient Overvoltages within a 345kV Korean Thermal Plant

  • Yeo, Sang-Min;Kim, Chul-Hwan
    • Journal of Electrical Engineering and Technology
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    • v.7 no.3
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    • pp.297-303
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    • 2012
  • This paper presents the simulation results for the analysis of a lightning surge, switching transients and very fast transients within a thermal plant. The modeling of gas insulated substations (GIS) makes use of electrical equivalent circuits that are composed of lumped elements and distributed parameter lines. The system model also includes some generators, transformers, and low voltage circuits such as 24V DC rectifiers and control circuits. This paper shows the simulation results, via EMTP (Electro-Magnetic Transients Program), for three overvoltage types, such as transient overvoltages, switching transients, very fast transients and a lightning surge.

Fault Classification in Phase-Locked Loops Using Back Propagation Neural Networks

  • Ramesh, Jayabalan;Vanathi, Ponnusamy Thangapandian;Gunavathi, Kandasamy
    • ETRI Journal
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    • v.30 no.4
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    • pp.546-554
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    • 2008
  • Phase-locked loops (PLLs) are among the most important mixed-signal building blocks of modern communication and control circuits, where they are used for frequency and phase synchronization, modulation, and demodulation as well as frequency synthesis. The growing popularity of PLLs has increased the need to test these devices during prototyping and production. The problem of distinguishing and classifying the responses of analog integrated circuits containing catastrophic faults has aroused recent interest. This is because most analog and mixed signal circuits are tested by their functionality, which is both time consuming and expensive. The problem is made more difficult when parametric variations are taken into account. Hence, statistical methods and techniques can be employed to automate fault classification. As a possible solution, we use the back propagation neural network (BPNN) to classify the faults in the designed charge-pump PLL. In order to classify the faults, the BPNN was trained with various training algorithms and their performance for the test structure was analyzed. The proposed method of fault classification gave fault coverage of 99.58%.

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Design of a Multi-Valued Arithmetic Processor with Encoder and Decoder (인코더, 디코오더를 가지는 다치 연산기 설계)

  • 박진우;양대영;송홍복
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.2 no.1
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    • pp.147-156
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    • 1998
  • In this paper, an arithmetic processor using multi-valued logic is designed. For implementing of multi-valued logic circuits, we use current-mode CMOS circuits and design encoder which change binary voltage-mode signals to multi-valued current-mode signals and decoder which change results of arithmetic to binary voltage-mode signals. To reduce the number of partial product we use 4-radix SD number partial product generation algorithm that is an extension of the modified Booth's algorithm. We demonstrate the effectiveness of the proposed arithmetic circuits through SPICE simulation and Hardware emulation using FPGA chip.

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Design of Low Noise Amplifier Utilizing Input and Inter Stage Matching Circuits (다양한 매칭 회로들을 활용한 저잡음 증폭기 설계 연구)

  • Jo, Sung-Hun
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.25 no.6
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    • pp.853-856
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    • 2021
  • In this paper, a low noise amplifier having high gain and low noise by using input and inter stage matching circuits has been designed. A current-reused two-stage common-source topology is adopted, which can obtain high gain and low power consumption. Deterioration of noise characteristics according to the source inductive degeneration matching is compensated by adopting additional matching circuits. Moreover trade-offs among noise, gain, linearity, impedance matching, and power dissipation have been considered. In this design, 0.18-mm CMOS process is employed for the simulation. The simulated results show that the designed low noise amplifier can provide high power gain and low noise characteristics.

Ultra-High Resolution and Large Size Organic Light Emitting Diode Panels with Highly Reliable Gate Driver Circuits

  • Hong Jae Shin
    • International journal of advanced smart convergence
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    • v.12 no.4
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    • pp.1-7
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    • 2023
  • Large-size, organic light-emitting device (OLED) panels based on highly reliable gate driver circuits integrated using InGaZnO thin film transistors (TFTs) were developed to achieve ultra-high resolution TVs. These large-size OLED panels were driven by using a novel gate driver circuit not only for displaying images but also for sensing TFT characteristics for external compensation. Regardless of the negative threshold voltage of the TFTs, the proposed gate driver circuit in OLED panels functioned precisely, resulting from a decrease in the leakage current. The falling time of the circuit is approximately 0.9 ㎲, which is fast enough to drive 8K resolution OLED displays at 120 Hz. 120 Hz is most commonly used as the operating voltage because images consisting of 120 frames per second can be quickly shown on the display panel without any image sticking. The reliability tests showed that the lifetime of the proposed integrated gate driver is at least 100,000 h.