• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2000년도 제15차 학술회의논문집
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• pp.56-56
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• 2000

In this paper, the relationship between GPS code and carrier tracking performance is given. Through the error analysis and experiments, the performance of code tracking loop can be improved using narrow correlation. The performance of code tracking loop can be also improved if the better carrier tracking loop is used. On the other hand, the performance of carrier tracking loop is independent of that of code tracking loop.

• 한국통신학회논문지
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• 제28권12A호
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• pp.983-990
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• 2003

본 논문에서는 3GPP 모뎀용 비동기식 동기추적회로(noncoherent code tracking loop)를 설계하고 설계된 회로의 정상상태 지터 분산(steady-state jitter variance)과 과도응답 특성(transient response characterisitc)을 해석한다. 먼저, AWGN 환경에서의 지터 분산을 펄스성형 필터(pulse-shaping filter), 타이밍 오프셋(timing offset), 신호 대잡음비(signal-to-interference ratio), 루우프 대역폭(loop bandwidth)에 대한 일반식으로 유도하고, 과도응답 특성을 이론적으로 해석한다. 이를 바탕으로, 디지털 하드웨어 구현이 용이한 가변 대역폭 동기추적회로를 설계하며 설계된 회로와 고정 대역폭 시스템의 성능을 이론적으로 비교, 분석하고 컴퓨터 시뮬레이션을 통해 검증한다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -1
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• pp.501-504
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• 2000

In this paper, performance of a pseudonoise (PN) code tracking loop is analyzed and simulated for a direct-sequence/code-division multiple access ( DS/CDMA) system with imperfect power control in a multipath fading channel. A noncoherent first-order delay-locked loop (DLL) is considered as a PN code tracking loop. Power control error is modeled as a log-normally distributed random variable. From the simulation results, it is shown that for smaller discriminator offset, tracking jitter performance is improved while MTLL performance is degraded. It is shown that large power control error and heavy shadowing substantially degrade the PN tracking performance. The analysis in this paper can be applicable to design of PN code tracking loop for a DS/CDMA system.

• 제어로봇시스템학회논문지
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• 제14권9호
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• pp.939-947
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• 2008

The GPS tracking loop consists of three parts in general: discriminator, loop filter and DCO (Digitally Controlled Oscillator). The loop filter is the main part of the tracking loop designed to ensure a good tracking performance. Generally, the loop filter is designed using classical PI(Proportional Integral) control. Although the carrier Doppler and code Doppler are generated by the same relative movement between the satellite and the user, often, the loop filters for each tracking loop are designed separately and independently. Sometimes, they are used in a combined manner such as carrier aided code tracking, FLL assisted PLL, etc. For better GPS signal tracking, we need to design the FLL/PLL/DLL altogether optimally. The purpose of this paper is to design a GPS receiver tracking loop based on the Kalman filter in a combined manner. Also, the proposed GPS receiver tracking loop is compared with a conventional tracking loop in terms of the transfer function and the DCO input. This paper shows that conventional tracking loop is equal to the Kalman filter based tracking loop.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(1)
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• pp.209-212
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• 2000

In this paper, effect of imperfect power control on performance of a pseudonoise (PN) code tracking loop is analyzed and simulated for a direct-sequence/code-division multiple access (DS/CDMA) system. The multipath fading channel is modeled as a two-ray Rayleigh fading model. Power control error is modeled as a log-normally distributed random variable. The tracking performance of DLL (delay-locked-loop) is evaluated in terms of tracking jitter and mean-time-to-lose-lock (MTLL). From the simulation results, it is shown that the PN tracking performance is very sensitive to the power control error.

• 한국항해항만학회:학술대회논문집
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• 한국항해항만학회 2006년도 International Symposium on GPS/GNSS Vol.2
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• pp.223-228
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• 2006

The main purpose of this paper is to describe the code tracking performance of a non-coherent digital delay lock loop (DLL) or coherent DLL while tracking GNSS signal in the presence of signal masking. The masking effect is usually caused by buildings that obscure the signal in either a periodic or random manner. In some cases, ideal masking is used to remove random or periodic interference. Three types of the masked signal are considered - no masking, periodic masking, and random masking of the signal input to the receiver. The mean time to lose lock (MTLL) of the code tracking loop are evaluated, and some numerical result and simulation results are reported. Finally, the steadystate tracking errors on the performance of the tracking loop in interference environment are also presented.

• 한국항행학회논문지
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• 제7권1호
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• pp.6-13
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• 2003

본 논문에서는 3GPP HSDPA 모뎀용 비동기식 동기추적회로를 설계하고, 설계된 동기추적회로에 대하여 정상상태 지터 분산과 타이밍 에러의 과도응답 특성을 이론적으로 분석하였다. 우선 AWGN 환경에서의 지터 분산을 펄스성형 필터, 타이밍 오프셋, 신호 대 잡음비, 루프 대역폭에 대한 식으로 유도하였으며, 과도응답 특성 또한 이론적으로 해석하였다. 끝으로 설계된 동기추적회로의 성능을 컴퓨터 시뮬레이션을 통하여 확인하였다.

• 한국항행학회논문지
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• 제1권1호
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• pp.70-80
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• 1997

본 논문에서는 CDMA 이동전파 환경에서 두 가지 비동기식 동기 추적 회로 즉, TCTL과 MCTL의 성능을 비교, 분석한다. 먼저, 두 가지 방식에 대해 안정 상태에서의 지터 분산을 펄스 성형 필터, 타이밍 오프셋, 신호 대 잡음 비 및 루우프 대역폭의 함수로 이론적으로 유도한다. 또한, 루우프 필터의 설계 방법에 대해 2차 동기 추적회로를 중심으로 고찰한다. 끝으로, 동기 추적 오차에 의한 BER 성능 저하를 ETRI 에 의해 IMT-2000용으로 설계된 CDMA 시스템의 역방향 링크에 대해 분석한다.

• 정보통신설비학회논문지
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• 제8권3호
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• pp.107-110
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• 2009

In this paper, a PN code tracking loop with extended Kalman filter (EKF) is proposed for a direct-sequence spread-spectrum. EKF is used to estimate amplitude and delay in a multipath. fading channel. It is shown that tracking error performance is significantly improved by EKF compared with a conventional tracking loop.

• 전자공학회논문지A
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• 제33A권5호
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• pp.165-171
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• 1996

A noncoherent full-digital PN(pseudo noise) code acquisition/tracking loop has been presetned and implemented in FPGA for the CDMA band-limited direct-sequence spread-spectrum (DS-SS) signals. It employs a simple decimator to control of local PN code phase to lower the hardware cost, and a second order loop to enable the more accurate tracking. The proposed acquisition/tracking loop has been designed in RTL-level VHDL, synthesized into logic gates using the design analyzer of synopsys software, implemented in an ALTERA FPGA chip, and tested. The number of logic gates used in the implemented FPGA chip is around 7000. The functionality has been verified using a PC interface circuitry and a logic analyzer.