• 전기학회논문지P
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• 제60권4호
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• pp.227-235
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• 2011

This paper describes a PMSM control algorithm for realizing a low-cost motor drive system using a general purpose microcontroller. The proposed sensorless algorithm consists of the current observer and the sensorless scheme based on instantaneous reactive power. Also the control board system is not the high-cost DSP(digital signal processor) system but the general purpose microcontroller and it allows to reduce the unit cost of the motor system. However the clock frequency of the proposed microcontroller is one-fifths for the clock frequency of the DSP. In addition, the switching frequency must be selected as the lower frequency because of complex mathematic modeling of the sensorless algorithm. the low switching frequency augments the noise of the motor and might make accurate speed control impossible. Thus this paper proposes the optimization method to supplement the drawback of the general purpose microcontroller and the usefulness of the proposed method is verified through the experiment.

• 대한전자공학회논문지
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• 제10권5호
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• pp.1-6
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• 1973

본논문은 자동급수기의 설계 및 제작연구를 한 것으로 digital scanning circuits를 이용하여 10개의 probe를 차례로 scanning하여 지표의 습도를 검출하여 reference level과 비교하여 필요한곳에 자동적으로 급수하도록 설계하였다. 이 system의 control을 위하여 main clock oscillator와 controloscillator를 사용하였고 control circuit로는 programmable unijunction transistor를 이용하여 reference level을 조절하게하여 임의의 원하는 습도에 급수하도록 하였다. 제작된 급수재는 모래의 습도가 6%에서 51%로 변화시키면서 실험하여 언제나 input level이 reference level보다 약 0.6V보다 높을때 완전동작하였으며 reference level은 임의로 조절할 수 있었다.

• 대한전자공학회논문지SD
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• 제39권4호
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• pp.72-83
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• 2002

본 논문에서는 공급 전압을 순수하게 소프트웨어적으로 제어함으로서, 하드웨어 구현이 간단하고 전력 소모를 효과적으로 줄이며 복잡한 인터페이스 회로가 필요 없는 새로운 저전력 VLSI 시스템 아키텍처를 제안하였다. 제안된 아키텍처는 클록 주파수-공급 전압 특성을 순수하게 소프트웨어적으로만 모델링하고, 시스템상의 여러 칩들에 대해서 각각 독립적으로 공급 전압을 제어하고, 주 클록 주파수 f/sub CLK/의 1/n인 f/sub CLK/, f/sub CLK/2, f/sub CLK/3...만을 클록 주파수로 허용하였다. 또한, 제안된 저전력 VLSI 시스템 아키텍처의 프로토타입 시스템을 제작하고 전력 소모를 측정하였다. 프로토타입 시스템은 기존의 상용 마이크로프로세서 평가 보드를 약간 수정하여 레벨 쉬프터와 전안 스위치와 같은 간단한 개별 소자만을 덧붙여서 제작되었으며, 0.58W이던 전력 소모가 0.12W로 감소함을 확인할 수 있었다.

• Reproductive and Developmental Biology
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• 제33권3호
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• pp.163-169
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• 2009

Many biological systems are regulated by an intricate set of feedback loops that oscillate with a circadian rhythm of roughly 24 h. This circadian clock mediates an increase in body temperature, heart rate, blood pressure, and cortisol secretion early in the day. Recent studies have shown changes in the amplitude of the circadian clock in the hearts and livers of streptozotocin (STZ)-treated rats. It is therefore important to examine the relationships between circadian clock genes and growth factors and their effects on diabetic phenomena in animal models as well as in human patients. In this study, we sought to determine whether diurnal variation in organ development and the regulation of metabolism, including growth and development during the juvenile period in rats, exists as a mechanism for anticipating and responding to the environment. Also, we examined the relationship between changes in growth factor expression in the liver and clock-controlled protein synthesis and turnover, which are important in cellular growth. Specifically, we assessed the expression patterns of several clock genes, including Per1, Per2, Clock, Bmal1, Cry1 and Cry2 and growth factors such as insulin-like growth factor (IGF)-1 and -2 and transforming growth factor (TGF)-${\beta}1$ in rats with STZ-induced diabetes. Growth factor and clock gene expression in the liver at 1 week post-induction was clearly increased compared to the level in control rats. In contrast, the expression patterns of the genes were similar to those observed after 5 weeks in the STZ-treated rats. The increase in gene expression is likely a compensatory change in response to the obstruction of insulin function during the initial phase of induction. However, as the period of induction was extended, the expression of the compensatory genes decreased to the control level. This is likely the result of decreased insulin secretion due to the destruction of beta cells in the pancreas by STZ.

• 제어로봇시스템학회논문지
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• 제20권6호
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• pp.669-675
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• 2014

In this paper, we described the investigated theoretical time synchronization performances and experiment results obtained by commercially provided PTP (Precise Time Protocol) modules when the time of a slave clock is synchronized to the master clock. In the case of the theoretical performance analysis, we investigated 3 types of clock levels such as Crystal Oscillator (XO), TCXO (Temperature Compensated XO) and OCXO (Oven Controlled XO). From the analysis, it was observed that the synchronization performance is greatly influenced by the synchronization period and the required performance under 1 us can be achieved by using XO level clocks when the synchronization period is less than 2 seconds and the uncertainty of the propagation delay is under 100 ns. For the experiments using commercial PTP modules, the synchronization performance was investigated for direct, through 1 hub and through 2 hubs connections between the master clock and the slave clock. From the experiment results, we observed that time synchronization under 90 ns with 1,000 seconds observation interval can be achieved in the case of direct connection.

• Journal of information and communication convergence engineering
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• 제10권2호
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• pp.187-193
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• 2012

A 1 GHz CMOS fast-lock phase-locked loop (PLL) is proposed to support the quick wake-up time of mobile consumer electronic devices. The proposed fast-lock PLL consists of a conventional charge-pump PLL, a frequency-to-digital converter (FDC) to measure the frequency of the input reference clock, and a digital-to-analog converter (DAC) to generate the initial control voltage of a voltage-controlled oscillator (VCO). The initial control voltage of the VCO is driven toward a reference voltage that is determined by the frequency of the input reference clock in the initial mode. For the speedy measurement of the frequency of the reference clock, an FDC with a parallel architecture is proposed, and its architecture is similar to that of a flash analog-to-digital converter. In addition, the frequency-to-voltage converter used in the FDC is designed simply by utilizing current integrators. The circuits for the proposed fast-lock scheme are disabled in the normal operation mode except in the initial mode to reduce the power consumption. The proposed PLL was fabricated by using a 0.18-${\mu}m$ 1-poly 6-metal complementary metal-oxide semiconductor (CMOS) process with a 1.8 V supply. This PLL multiplies the frequency of the reference clock by 10 and generates the four-phase clock. The simulation results show a reduction of up to 40% in the worstcase PLL lock time over the device operating conditions. The root-mean-square (rms) jitter of the proposed PLL was measured as 2.94 ps at 1 GHz. The area and power consumption of the implemented PLL are $400{\times}450{\mu}m^2$ and 6 mW, respectively.

• 한국전자파학회논문지
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• 제27권12호
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• pp.1097-1104
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• 2016

적외선 카메라는 Mil-Std-461 항목 중 복사성 방사 잡음 시험, RE-102의 규격 만족에 어려움을 겪는다. 특히 무인항공기용 전자장비의 경우 차폐 케이블을 사용하지 않아 전자기적합성 규격 만족이 어려워 적절한 대응 설계가 필요하다. 무인정찰기용 적외선 카메라의 RE-102 시험 중 50~200 MHz 대역에서 30 dBuV/m 이상 규격을 초과하는 방사 잡음을 확인하였다. Pcb em scan 결과, 디지털 제어 신호 클록의 체배 주파수에 의한 첨두 잡음 발생을 확인하였고, 카메라의 제어 클록에 3 % 다운 스프레딩 방식의 확산 스펙트럼 클록 생성기를 적용하여 방사 잡음이 최대 22.9 dBuV/m 감소함을 확인하였다.

• 한국통신학회논문지
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• 제23권8호
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• pp.2064-2071
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• 1998

휴대용 기기에서 자체 발진하여 클럭원으로 사용되는 TCXO의 출력과 같은 작은 진폭(400mV)의 정현파 입력을 내부 논리회로의 클럭원으로 사용하기 위한 파형정형 및 50%의 듀티 비(duty ratio)의 출력을 가지는 새로운 디지털 클럭레벨 변환기를 설계, 개발 하였다. 정, 부 두 개의 비교기, RS 래치, 차아지 펌프, 기준 전압 발생기로 구성된 새로운 신호 변환회로는 출력파형의 펄스 폭을 감지하고, 이 결과를 궤환루프로 구성하여 입력 비교기 기준 전압단자로 궤환시킴으로서 다지털 신호레벨의 정확한 50%의 듀티 비를 가진 출력을 생성할 수 있다. 개발한 레벨변환기는 ADC등의 샘플링 클럭원, PLL 또는 신호 합성기의 클럭원으로 사용할 수가 있다. 설계는 $0.8\mu\textrm{m}$ double metal double poly analog CMOS 공정을 사용하고, BSIM3 model을 사용하였으며, 실험결과 370mV의 정현파 입력율 50 + 3%의 듀티 비를 가진 안정된 논리레벨 출력 동작특성을 얻을 수 있었다.

• 한국농공학회지
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• 제41권2호
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• pp.37-43
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• 1999

This study was conducted to develop the simple and convenient irrigation control model which can maintain the appropriate rates of irrigation and drainage of nutrient solution according to the enviornmental conditions and growth stages in soilless culture of cucumber. In order to obtain fundamental data for development of the model, investigation of the actual state of soilless culture practices was carried out. Most irrigatioin systems of soillness culture were controlled by the time colock. Evapotranspiration of cucumber in soilness culture was investigated and correlations with environmental conditions were analyzed , and its estimating model was developed. In order to develop the irrigation system which can control the amount of nutrient solution applied according to seasons, weather conditions, and growth stages, a irrigation clock control was developed. Applicability of the model was tested by simulation. Drainage rates of nutrient solution controlled by conventional time clock, integrated solar radiation, and the developed model were 61% , 20%, and 32% , respectively in cucumber perlite culture.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 B
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• pp.677-680
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• 2003

In this paper, the analysis of practical end-to-end delay in worst case is performed for distributed control system considering the implementation of the system. The control system delay is composed of the delay caused by multi-task scheduling of operating system, the delay caused by network communication, and the delay caused by the asynchronous between them. Through simulation tests based on CAN(Controller Area Network), the proposed end-to-end delay in worst case is validated. Additionally, online clock synchronization algorithm is proposed here for the control system. Through another simulation test, the online algorithm is proved to have better performance than offline one in the view of network bandwidth utilization.