• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.405-414
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• 2016

IC-implementations provide high performance for solving the high computational cost of pattern matching but have relative low flexibility for satisfying different applications. In this paper, we report an associative memory architecture for k nearest neighbor (KNN) search, which is one of the most basic algorithms in pattern matching. The designed architecture features reconfigurable vector-component parallelism enabled by programmable switching circuits between vector components, and a dedicated majority vote circuit. In addition, the main time-consuming part of KNN is solved by a clock mapping concept based weighted frequency dividers that drastically reduce the in principle exponential increase of the worst-case search-clock number with the bit width of vector components to only a linear increase. A test chip in 180 nm CMOS technology, which has 32 rows, 8 parallel 8-bit vector-components in each row, consumes altogether in peak 61.4 mW and only 11.9 mW for nearest squared Euclidean distance search (at 45.58 MHz and 1.8 V).

• Proceedings of the IEEK Conference
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• summer
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• pp.122-127
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• 2004

The color gamut mapping method that is used for enhancing the color reproduction quality between PC monitor and printer devices is adopted for display quality enhancement. The high definition display devices operate at the clock speed of around $70\;MHz\;\sim\;150\;MHz$ and permit several nano seconds for real-time processing. Thus, the concept of three-dimensional reduced resolution look-up table is used. The required hardware can be greatly reduced by look-up table resolution adjustment. The proposed hardware architecture is successfully implemented in ASIC and also successfully adopted in display quality enhancement purposes.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.5
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• pp.225-233
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• 2004

A novel real-time color gamut mapping method is described. The color gamut mapping method that is used for enhancing the color reproduction quality between PC monitor and printer devices is adopted for digital TV display quality enhancement. The high definition digital TV display devices operate at the clock speed of around 70MHz ～ 150MHz and permit several nano seconds for real-time gamut mapping. Thus, the concept of three-dimensional reduced resolution look-up table is introduced for real-time processing. The required hardware can be greatly reduced by look-up table resolution adjustment. The proposed hardware architecture is successfully implemented in FPGA and ASIC and also successfully adopted in digital TV display quality enhancement purposes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.22-30
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• 2009

Due to high levels of integration and complexity, the Network-on-Chip (NoC) approach has emerged as a new design paradigm to overcome on-chip communication issues and data bandwidth limits in conventional SoC(System-on-Chip) design. In particular, exponentially growing of energy consumption caused by high frequency, synchronization and distributing a single global clock signal throughout the chip have become major design bottlenecks. To deal with these issues, a globally asynchronous, locally synchronous (GALS) design combined with low power techniques is considered. Such a design style fits nicely with the concept of voltage-frequency-islands (VFI) which has been recently introduced for achieving fine-grain system-level power management. In this paper, we propose an efficient design methodology that minimizes energy consumption by VFI partitioning on an NoC architecture as well as assigning supply and threshold voltage levels to each VFI. The proposed algorithm which find VFI and appropriate core (or processing element) supply voltage consists of traffic-aware core graph partitioning, communication contention delay-aware tile mapping, power variation-aware core dynamic voltage scaling (DVS), power efficient VFI merging and voltage update on the VFIs Simulation results show that average 10.3% improvement in energy consumption compared to other existing works.