• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.3C
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• pp.398-407
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• 2004

In this paper, a blind watermarking method which is suitable to the video compression using 2-D discrete wavelet transform was proposed and implemented into the hardware using VHDL(VHSIC Hardware Description Language). The goal of the proposed watermarking algorithm is the authentication about the manipulation of the watermark embedded image and the detection of the error positions. Considering the compressed video image, the proposed watermarking scheme is unrelated to the quantization and is able to concurrently embed or extract the watermark. We experimentally verified that the lowest frequency subband(LL4) is not sensitive to the change in the spatial domain, so LL4 subband was selected for the mark space. And the combination of the bitplanes which has the properties of both the minimum degradation of the image and the robustness was chosen as the embedded Point in the mark space in LL4 subband. Since we know the watermark embedded positions and the watermark is embedded by not varying the value but changing the value, the watermark can be extracted without the original image. Also, for the security when exposing the watermark embedded position, we embed the encrypted watermark by the block cipher. The proposed watermark algorithm shows the robustness against the general image manipulation and is easily transplanted into the image or video compressor with the minimal changing in the structure. The designed hardware has 4037 LABs(24％) and 85 ESBs(3％) in APEX20KC EP20K400CF672C7 FPGA of Altera and stably operates in 82MHz clock frequency.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.1
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• pp.62-74
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• 2008

In this paper, we would like to propose the design of symmetric digital filter core in order to use in the radio astronomy. The function of FIR filter core would be designed by VHDL code required at the Data Acquisition System (DAS) of Korean VLBI Network (KVN) based on the FPGA chip of Vertex-4 SX55 model of Xilinx company. The designed digital filter has the symmetric structure to increase the effectiveness of system by sharing the digital filter coefficient. The SFFU(Symmetric FIR Filter Unit) use the parallel processing method to perform the data processing efficiently by using the constrained system clock. In this paper, therefore, for the effective design of SFFU, the Unified Synthesis software ISE Foundation and Core Generator which has excellent GUI environment were used to overall IP core synthesis and experiments. Through the synthesis results of digital filter core, we verified the resource usage is less than 40% such as Slice LUT and achieved the maximum operation frequency is more than 260MHz. We also confirmed the SFFU would be well operated without error according to the SFFU simulation result using the Modelsim 6.1a of Mentor Graphics Company. To verify the function of SFFU, we carried out the additional simulation experiments using the pseudo signal to the Matlab software. From the comparison experimental results of simulation and the designed digital FIR filter, we confirmed the FIR filter was well performed with filter's basic function. So we verified the effectiveness of the designed FIR digital filter with symmetric structure using FPGA and VHDL.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.9
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• pp.13-19
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• 2008

Time synchronization of nodes in sensor network synchronizes sensor nodes to one time clock. This is very essential in sensor networks so that the information collected and reported from the sensor nodes becomes meaningful. If sensor nodes are not synchronized, disaster report with time information can be wrong analyzed and this may lead to big calamity. With the limitation of battery and computing power, time synchronization algorithm imported in sensor nodes has to be as simple as it doesn't need big complexity, nor generates many synchronization messages. To reduce the synchronization error, hop count should be kept small between reference node to initiate synchronization and sensor nodes to be synchronized. Therefore, multiple reference nodes are used instead of single reference node. The use of multiple reference nodes introduce the requirement of synchronization among reference nodes in the network. Several algorithms have been proposed till now, but the synchronization among reference nodes are not well considered. This paper proposes improved time synchronization for sensor networks by synchronizing multiple reference nodes inside the network. Through simulation, we validated the effects of new algorithm.