• 한국전산유체공학회:학술대회논문집
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• 2008.03b
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• pp.105-106
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• 2008

As a carrier of malaria and sneak of blood, mosquitoes are an unpleasant insect. However, there are several unknown natural secretes related with mosquitoes. Among them, we focused on the blood sucking process of a female mosquito. The main objective of this study is to understand the mosquito's blood sucking mechanism that can be used to resolve the problem encountered in the injection or transport of infinitesimal biological fluids in a micro-chip. At first, the velocity fields of blood-sucking flow in a proboscis were measured using a micro-particle image velocimetry (PIV) technique. The velocity signals of flow in the proboscis show periodic variation. This seems to be resulted from the beating of the pharyngeal pump which works as driving power. To analyze the pumping mechanism, the temporal variation of the pharyngeal pump was visualized using the synchrotron X-ray micro-imaging technique. The volume variation was estimated by the help of digital image processing techniques. Once the main mechanism of blood sucking process was found, a effective micro-pumping system with high efficiency would be developed in near future.

• Journal of information and communication convergence engineering
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• v.18 no.1
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• pp.1-7
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• 2020

This paper proposes a fast-processing and low-cost hardware multiple input multiple output (MIMO) channel emulator. The channel emulator is an important component of hardware-based simulation systems. The novelty of this work is the use of sharing and pipelining functions to reduce hardware resource utilization while maintaining a high sample rate. In our proposed emulator, the samples are created sequentially and interpolated to ensure the sample rate is equal to the base band rate. The proposed 4 × 4 MIMO requires low-cost hardware resource so that it can be implemented on a single field-programmable gate array (FPGA) chip. An implementation on Xilinx Virtex-7 VX980T was found to occupy 10.47% of the available configurable slice registers and 12.58% of the FPGA's slice lookup tables. The maximum frequency of the proposed emulator is 758.064 MHz, so up to 560 different paths can be processed simultaneously to generate 560 × 758 million × 2 × 32 bit complex-valued fading samples per second.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12B
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• pp.1637-1647
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• 2001

Multi-Code CDMA (MC-CDMA) can not only be integrated easily with a conventional system, but also achieve good spectral efficiency and high processing gain. However, it suffers from high value of peak-to-average power ratio (PAPR). In this paper, we propose the Multi-Phase CDMA (MP-CDMA) system that can provide variable rate service and is not susceptible to the non-linear characteristics of amplifier. The clipping is introduced between at the output of multi-code modulator and at the input of MPSK modulator in order to improve the performance of MPSK chip demodulator and reduce the system complexity, The system performances are compared for the different Number of codes and different clipping levels, respectively. The optimum clipping level is also evaluated for the different number of codes in both, AWGN and frequency flat fading channel.

• Journal of Biosystems Engineering
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• v.31 no.5 s.118
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• pp.403-409
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• 2006

This study was performed to design a peeling device for root crop that were considered of the three possible types such as blade belt type, brush type, and rotating blade type, and to inspect the characteristics of the experimented peeling methods based on the chonggag (altari) radish tests. The peeling performances by the blade belt type and brush type devices were not established so well with the troublesome like adhesion of the chip on the blades was occurred, and the difficulties to produce the blade parts were come out on these types of the peeling devices. But the peeling operations by the rotating blade type peeling device was completed without needs to clean blades, and it was concluded that it would be possible to practical mechanization of the root crop which shaped similar chonggag radish for it's constructional simplicity and feasibility.

• Journal of the Korean Society for Precision Engineering
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• v.22 no.7 s.172
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• pp.27-37
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• 2005

Direct writing technology on the silicon wafer surface is used to reduce the size of the chip as the miniature trend in electronic circuit. In order to improve the productivity and efficiency, the real time quality estimation is very important in each semiconductor process. In laser marking, marking quality is determined by readability which is dependant on the contrast of surface, the line width, and the melting depth. Many researchers have tried to find theoretical and numerical estimation models fur groove geometry. However, these models are limited to be applied to the real system. In this study, the estimation system for the line width during the laser marking was proposed by process monitoring method. The light intensity emitted by plasma which is produced when irradiating the laser to the silicon wafer was measured using the optical sensor. Because the laser marking is too fast to measure with external sensor, we build up the coaxial monitoring system. Analysis for the correlation between the acquired signals and the line width according to the change of laser power was carried out. Also, we developed the models enabling the estimation of line width of the laser marking through the statistical regression models and may see that their estimating performances were excellent.

• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.22 no.2
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• pp.170-178
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• 2012

This paper is concerned with the development of power amplifier and controller for piezoelectric actuator and sensor used in smart structures. Even though a high-voltage power amplifier is provided in the form of an operational amplifier, a very high DC voltage is still necessary as a power supply. In this study, we propose a low-cost design for the power amplifier including the DC power supply. We also need a controller on which a control algorithm will be mounted. In general, a digital signal processing chip is popularly used because of high speed. However, only commercial product is available for smart structure applications. In this paper, a controller consisting of a DSP and electronic circuits suitable for piezoelectric sensor and actuator pair is proposed. To validate the proposed controller with power amplifier, experiment on smart structure was carried out. The experimental results show that the proposed control system can be effectively used for smart structure applications with low cost.

• Journal of the Korea Society of Computer and Information
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• v.11 no.2 s.40
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• pp.35-42
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• 2006

In this paper we implement a new simulator for performance analysis of a parallel digital signal processing distributed shared memory multiprocessor systems. using Parsec The key idea of this simulator is suitable in simulation of system that uses DMA function of TMS320C6701 DSP chip and local memory which have fast access time. Also, because correction of performance parameter and reconfiguration for hardware components are easy, we can analyze performance of system in various execution environments. In the simulation, FET, 2D FET, Matrix Multiplication. and Fir Filter, which are widely used DSP algorithms. have been employed. Using our simulator, the result has been recorded according to different the number of processor, data sizes, and a change of hardware element. The performance of our simulator has been verified by comparing those recorded results.

• Journal of Korea Society of Digital Industry and Information Management
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• v.15 no.4
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• pp.31-40
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• 2019

This paper proposes an adaptive PCIe system for TI C66x DSPs. Conventionally, the PCIe system provided by the C66x is a system dependent on the structure in which the primary core writes an application to the DSP memory through the PCIe interface, then activate the secondary core. Due to the dependency between the cores, when developing a project using a PCIe interface, the remaining cores have to be programmed with a concern of the primary core used as the PCIe interface. Therefore, in order to de-couple the connections among the cores, an adaptive PCIe system is proposed, in the paper, in which the cores operate independently compared to the conventional system. Since the core used as the PCIe interface only runs PCIe related operations in the new system, the remaining cores can be fully utilized without concerning the connections with the core for PCIe interface. In order to verify the feasibility of the proposed adaptive PCIe system, the implementations of LTE-A down link, and IEEE 802.11ac are carried out using the evaluation board which includes a TMS320C6670 chip. Altogether, these results support that we demonstrated that the digital signal processing systems with the PCIe Interface can be developed more rapidly by applying the proposed system.

• Journal of Satellite, Information and Communications
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• v.5 no.2
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• pp.92-96
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• 2010

We propose a new satellite OFDMA(Orthogonal Frequency Division Multiple Access) scheme with greatly enhanced tolerance of timing offset among the users. In uplink OFDMA systems, timing misalignment among users destroys subcarrier orthogonality and thus, it degrades the performance. In order to avoid this performance degradation, the accurate processing, so called 'ranging', is required to synchronize among users. However, ranging scheme is not available in the satellite systems due to the very long round trip delay. Exploiting the property that PSW(Propoerly Scrambled Walsh-code) code has zero correlation despite ${\pm}1$ chip timing offset, the proposed OFDMA achieves MAI free performance with the timing offset up to ${\pm}1$ OFDM symbol duration for the satellite systems.

• ETRI Journal
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• v.34 no.2
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• pp.216-225
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• 2012

This paper presents a transceiver module for human body communications whereby a spread signal with a group of 64 Walsh codes is directly transferred through a human body at a chip rate of 32 Mcps. Frequency selective digital transmission moves the signal spectrum over 5 MHz without continuous frequency modulation and increases the immunity to induced interference by the processing gain. A simple receiver structure with no additional analog circuitry for the transmitter has been developed and has a sensitivity of 250 ${\mu}V_{pp}$. The high sensitivity of the receiver makes it possible to communicate between mobile devices using a human body as the transmission medium. It enables half-duplex communication of 2 Mbps within an operating range of up to 170 cm between the ultra-mobile PCs held between fingertips of each hand with a packet error rate of lower than $10^{-6}$. The transceiver module consumes 59 mA with a 3.3 V power supply.