• 대한기계학회논문집
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• 제14권6호
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• pp.1515-1522
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• 1990

본 연구에서는 천연다이아몬드의 인선형상을 R형과 S형으로 구분하여 제작하 고 미세이송과 절삭속도 변화를 주어 이에 얻어지는 표현거칠기, 칩 생성기구 및 경면 성을 검토하였다.

• 한국전자파학회지:전자파기술
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• 제24권2호
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• pp.51-57
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• 2013

The current expanding mobile markets incessantly demands small form factor, low power consumption and high aggregate throughput for silicon-level integration such as memory to logic system. One of emerging solution for meeting this high market demand is 3D through silicon stacking (TSS) technology. Main challenges to bring 3D TSS technology to the volume production level are establishing a cost effective supply chain and building a reliable manufacturing processes. In addition, this technology inherently help increase number of IOs and shorten interconnect length. With those benefits, however, potential signal and power integrity risks are also elevated; increase in PDN inductance, channel loss on substrate, crosstalk and parasitic capacitance. This paper will report recent progress of wide IO memory to high count TSV logic device assembly development work. 28 nm node TSV test vehicles were fabricated by the foundry and assembled. Successful integration of memory wide IO chip with less than a millimeter package thickness form factor was achieved. For this successful integration, we discussed potential signal and power integrity challenges. This report demonstrated functional wide IO memory to 28 nm logic device assembly using 3D package architecture with such a thin form factor.

• ETRI Journal
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• 제42권4호
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• pp.480-490
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• 2020

More than 42 000 fires occur nationwide and cause over 2500 casualties every year. There is a lack of specialized equipment, and rescue operations are conducted with a minimal number of apparatuses. Through-the-wall radars (TTWRs) can improve the rescue efficiency, particularly under limited visibility due to smoke, walls, and collapsed debris. To overcome detection challenges and maintain a small-form factor, a TTWR system-on-chip (SoC) and its architecture have been proposed. Additive reception based on coherent clocks and reconfigurability can fulfill the TTWR demands. A clock-based single-chip infrared radar transceiver with embedded control logic is implemented using a 130-nm complementary metal oxide semiconductor. Clock signals drive the radar operation. Signal-to-noise ratio enhancements are achieved using the repetitive coherent clock schemes. The hand-held prototype radar that uses the TTWR SoC operates in real time, allowing seamless data capture, processing, and display of the target information. The prototype is tested under various pseudo-disaster conditions. The test standards and methods, developed along with the system, are also presented.

• 전기전자학회논문지
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• 제13권2호
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• pp.101-107
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• 2009

집적회로의 공정기술 및 설계기술이 발전함에 따라 많은 IP가 하나의 반도체 칩에 집적되어 하나의 시스템을 구성하는 SoC 설계가 많이 이루어지고 있다. 본 논문에서는 다양한 IP 간에 효율적인 데이터 통신이 이루어지도록 버스 상의 전송 특성에 따라 버스모드를 동적으로 재구성하는 SoC 3중 버스 구조를 제안한다. 제안된 버스는 다중-단일버스 모드, 단일-다중버스 모드로 재구성이 가능하며 따라서 단일버스 모드와 다중버스 모드의 장점을 모두 갖는다. 실험결과 제안된 버스구조는 기존의 고정된 버스구조보다 독립적이며 데이터 전송시간을 단축시킬 수 있음을 확인하였다. 그리고 제안된 버스구조를 JPEG 시스템에 적용한 결과 다중버스구조보다 평균 22%의 전송시간 단축을 얻을 수 있었다.

• 마이크로전자및패키징학회지
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• 제24권4호
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• pp.91-95
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• 2017

Package-On-Package (PoP) technology is developing toward smaller form factors with high-speed data transfer capabilities to cope with high DDR4x memory capacity. The common application processor (AP) used for PoP devices in smartphones has the bottom package as logic and the top package as memory, which requires both thermally and electrically enhanced functions. Therefore, it is imperative that PoP designs consider both thermal and power distribution network (PDN) issues. Stacked packages have poorer thermal dissipation than single packages. Since the bottom package usually has higher power consumption than the top package, the bottom package impacts the thermal budget of the top package (memory). This paper investigates the thermal and electrical characteristics of PoP designs, particularly the bottom package. Findings include that via and dense via-cluster volume have an important role to lower thermal resistance to the motherboard, which can be an effective way to manage chip hot spots and reduce the thermal impact on the memory package. A Cu block and dense via-cluster layout with an optimal location are proposed to drain the heat from the chip hot spots to motherboard which will enhance thermal and electrical performance at the design stage. The analytical thermal results can be used for design guidelines in 3D packaging.

• International Journal of Precision Engineering and Manufacturing
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• 제2권2호
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• pp.38-47
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• 2001

This paper decribes the development of computer-aided design of a very precise progressice die for lead frame of semiconductor chip. The approach to the system is based on knowledgr-based rules. Knowledge of fie이 experts. This system has been written in AutoLISP using AutoCAD ona personal computer and the I-DEAS drafting programming Language on the I-DEAS mater series drafting with on HP9000/715(64) workstation. Data exchange between AutoCAD and I-DEAS master series drafting is accomplished using DXF(drawing exchange format) and IGES(initial graphics exchange specification) files. This system is composed of six main modules, which are input and shape treatment, production feasibility check, strip layout, data conversion, die layout, and post processing modules. Based on Knowledge-based rules, the system considers several factors, such as V-notches, dimple, pad chamfer, spank, cavity punch, camber, coined area, cross bow, material and thickness of product, complexities of blank geometry and punch profiles, specifications of available presses, and the availability of standard parts. As forming processes and the die design system using 2D geometry recognition are integrated with the technology of process planning, die design, and CAE analysis, the standardization of die part for lead frames requiting a high precision process is possible. The die layout drawing generated by the die layout module s displayed in graphic form. The developed system makes it possible to design and manufacture lead frame of a semiconductor more efficiently.

• 한국전자파학회논문지
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• 제19권8호
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• pp.940-945
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• 2008

본 논문에서는 능동 위상 배열 레이다 시스템에 적용 가능한 브릭형 구조의 능동 송수신 모듈을 설계 및 제작하였다. 제안한 브릭형 구조의 능동 송수신 모듈은 MCM(Multi-Chip Module) 형태이며, 타일형 능동 송수신 모듈에 적용할 수 있도록 하기 위하여 캐비티 구조와 주요 특성을 만족하도록 설계하였다. 제작한 브릭형 능동 송수신 모듈의 시험을 통하여 목표로 한 전기적 특성을 만족함을 확인하였으며, 능동 위상 배열 레이다에 운용 가능성을 확인하였다.

• 전력전자학회논문지
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• 제9권1호
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• pp.88-95
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• 2004

스테핑 모터의 위치 분해능을 향상하고 기계적 공진을 방지하기 위한 제어방법으로 마이크로 스텝 구동방식이 많이 이용되고 있다. 이론적인 마이크로 스텝 구동방식은 정현파를 기준신호로 사용하며, 마이크로프로세서 및 ROM을 사용함으로써 구동회로가 복잡하고, 가격이 증가하는 단점을 가지게 된다. 본 연구에서는 기준신호를 사다리꼴 파형으로 사용함으로써 제어회로를 간략화하고 저가의 제어장치로 마이크로 스테핑 구동방식을 구현하는 방법을 제안하고 있다. 제안한 방식을 검증하기 위하여 저가의 CPLD(EPM9320RC208-15)를 이용하여 구동장치를 구성하였으며, 실험을 통하여 기존의 방식과 성능을 비교하였다. 또한 CPLD 내부에 고속검출회로를 구현하여 고속 구동시 모터의 탈조를 방지하였다.

• 전기학회논문지
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• 제63권1호
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• pp.85-91
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• 2014

As RFID is utilized more frequently and diversely in terms of its application areas, the application of mobile RFID technology, which integrates cellular networks and RFID, is highly anticipated. The growth and development of the RFID field has bolstered the development of mobile RFID chips to be embedded in mobile phones. Because mobile RFID chips are embedded in cell phones, limitations such as low power, small form factor, and costliness must be confronted. This study presents the design of a RFID digital baseband processor that is suitable for mobile readers. The RF analog component, which affects the baseband signals, is designed separately, in consideration of the limitations stated above. The function of the baseband processor was verified through simulations and prototyped using FPGA. The power consumption of the chip is 20mW under a 20MHz clock and the chip measures $3mm{\times}3mm$.

• BioChip Journal
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• 제12권4호
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• pp.280-286
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• 2018

Hydrogel scaffolds composed of multiple components are promising platform in tissue engineering as a transplantation materials or artificial organs. Here, we present a new fabrication method for implementing multi-layered macroscopic hydrogel scaffold composed of multiple components by controlling height of hydrogel layer through precise control of ultraviolet (UV) energy density. Through the repetition of the photolithography process with energy control, we can form several layers of hydrogel with different height. We characterized UV energy-dependent profiles with single-layered PEGDA posts photocrosslinked by the modular methodology and examined the optical effect on the fabrication of multi-layered, macroscopic hydrogel structure. Finally, we successfully demonstrated the potential applicability of our approach by fabricating various macroscopic hydrogel constructs composed of multiple hydrogel layers.