• Title/Summary/Keyword: capacitance ratio

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Numerical Algorithm for Power Transformer Protection

  • Park, Chul-Won;Suh, Hee-Seok;Shin, Myong-Chul
    • KIEE International Transactions on Power Engineering
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    • v.4A no.3
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    • pp.146-151
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    • 2004
  • The most widely used primary protection for the internal fault detection of the power transformer is current ratio differential relaying (CRDR) with harmonic restraint. However, the second harmonic component could be decreased by magnetizing inrush when there have been changes to the material of the iron core or its design methodology. The higher the capacitance of the high voltage status and underground distribution, the more the differential current includes the second harmonic during the occurrence of an internal fault. Therefore, the conventional second harmonic restraint CRDR must be modified. This paper proposes a numerical algorithm for enhanced power transformer protection. This algorithm enables a clear distinction regarding internal faults as well as magnetizing inrush and steady state. It does this by analyzing the RMS fluctuation of terminal voltage, instantaneous value of the differential current, RMS changes, harmonic component analysis of differential current, and analysis of flux-differential slope characteristics. Based on the results of testing with WatATP99 simulation data, the proposed algorithm demonstrated more rapid and reliable performance.

The Optimal Circuit Condition Selection for Cable Charging Current Test by IEC60265-1 (IEC60265-1에 의한 케이블 충전전류 시험을 위한 최적 회로 조건 선정)

  • Kim, K.D.;Hur, Y.S.;Yun, J.H.;Lee, H.C.;Ham, G.H.;Park, J.H.
    • Proceedings of the KIEE Conference
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    • 2001.07a
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    • pp.264-266
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    • 2001
  • We must consider resistance capacitance and their circuit connection condition for cable charging current test by IEC60265-1. According to their values and circuits, the ratio of applied voltage and transient recovery voltage are much different. This paper is convinced of TRV waves and proposes the optical circuit required at the standard via the simulation of all circuit conditions.

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Performance Test of 200-MW Pulse Transformer for 80-MW Klystron Load (80-MW 클라이스트론 부하용 200-MW 펄스 트랜스포머의 성능시험)

  • Jang, S.D.;Oh, J.S.;Son, Y.G.;Cho, M.H.
    • Proceedings of the KIEE Conference
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    • 1999.07e
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    • pp.2167-2169
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    • 1999
  • A pulse transformer producing pulses with the peak power of 200-MW (400 kV 500 A at load side with $4.4{\mu}s$ flat-top) is required to drive the 80-MW pulsed klystron in the PLS linac. We have designed and manufactured the high power pulse transformer with 1 : 17 turn ratio. Its primary functions are to match the impedance of klystron tube to the modulators, and to provide step-up of the voltage. To obtain a fast rise time of the pulse voltage. Low leakage inductance and low distributed capacitance design is very important. In this paper, we discuss the equivalent circuit analysis of the pulse transformer, and present the full power performance test results of pulse transformer.

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Design of A High Energy Density Pulse Transformer (고 에너지 밀도 펄스 변압기 설계)

  • Nam, S.H.;Park, S.S.;Ha, K.M.
    • Proceedings of the KIEE Conference
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    • 1999.07e
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    • pp.2186-2188
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    • 1999
  • A high frequency and energy density pulse transformer is a critical component of a high voltage power supply in a traveling wave tube (TWT) amplifier system. In this paper, processes of design, manufacturing, and test of the transformer are discussed. Primary voltage of the transformer is 240 V. The transformer secondary have two outputs which are 4100 V (Helix) and 2050 V (Collector). Total output power is 860 W. Normal operating frequency of the transformer is 10 kHz. In high energy density pulse transformers, temperature rise is a main problem during its operation. From our study, it was found that resonant current due to leakage inductance and stray capacitance was the main cause of temperature rise. This happens because of the inherently high turn-ratio in high voltage transformers. Solutions to reduce stray components are presented.

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Optimal Conditions of Braille Recognition System Using Electrical Stimulus (전기자극을 이용한 점자인식장치의 최적조건)

  • Lee, Seungjik;Shin, Jaeho;Shin, Jaeho
    • Journal of Biomedical Engineering Research
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    • v.17 no.3
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    • pp.373-378
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    • 1996
  • In this paper, we calculated chronaxy value in order to determine the optimal conditions and stimulus pulse of information transmission. We also developed an electrical equivalent circuit of the hand including the contact part, which consists of two resistors (a contact resistor and finger resistor) and a capacitor. The minimum recoulition voltage was measured by using electrical stimulus. We found that the ranges of the above two resistances and the capacitance are 30-130k$\Omega$, 20-60k$\Omega$ and 10-30nF respectively. We found that the minimum recoulition voltage was the lowest at 100-300Hz and 10% of the duty ratio.

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Study on Controlling Pretilt Angle and Electrical Characteristics in ECB cell by Polymerized Reactive Mesogen monomer (ECB 셀에서 UV 경화성 RM 단분자에 의한 선경사각 조절 및 전기적 특성에 관한 연구)

  • Jeon, Eun-Jeong;Kim, Seong-Su;Lim, Young-Jin;Lee, Myoung-Hoon;Lee, Seung-Hee
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.06a
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    • pp.397-398
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    • 2008
  • We have studied the electrically controlled birefringence (ECB) mode using reactive mesogen (RM) monomer to control pretilt angle and improve electrical characteristics. The measure of capacitance confirmed new pretilt angle by RM monomer, and Voltage Holding Ratio (VHR) was increased more than normal ECB cell.

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Silicon Nitride Films Prepared at a Low Temperature (${\leq}200^{\circ}C$) for Gate Dielectric of Flexible Display

  • Lee, Kyoung-Min;Hwang, Jae-Dam;Lee, Youn-Jin;Hong, Wan-Shick
    • 한국정보디스플레이학회:학술대회논문집
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    • 2009.10a
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    • pp.1402-1404
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    • 2009
  • The silicon nitride films for gate dielectric were deposited by catalytic chemical vapor deposition at low temperature (${\leq}200^{\circ}C$). The mixture of $SiH_4$, $NH_3$ and $H_2$ was used as source gases. The current-voltage (I-V) and the capacitance-voltage (C-V) characteristics of the films were measured. The breakdown voltage and the flat band voltage shift of samples were improved by increase of the $NH_3$ contents and $H_2$ dilution ratio. The defect states were analyzed by photoluminescence (PL) spectra. As the defect states decreased, the breakdown voltage and the flat band voltage shift increased.

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Dual Path Magnetic-Coupled AC-PDP Sustain Driver with Low Switching Loss

  • Lee Jun-Young
    • Journal of Power Electronics
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    • v.6 no.3
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    • pp.205-213
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    • 2006
  • A cost-effective magnetic-coupled AC-PDP sustain driver with low switching loss is proposed. The transformer reduces current stress in the energy recovery switches which affects circuit cost and reliability. The turns-ratio can be used to adjust the sustain pulse slopes which affect gas discharge uniformity. Dividing the recovery paths prevents abrupt changes in the output capacitance and thereby switching losses of the recovery switches is reduced. In addition, the proposed circuit has a more simple structure because it does not use the recovery path diodes which also afford a large recovery current. By reducing the current stress and device count in the energy recovery circuit, the proposed driver may have decreased circuit cost and improved circuit reliability.

DC Bias Circuit and CTR Design of Off-Line Current-Mode-Controlled Flyback Converters with Optocoupler Isolation (Optocoupler 절연을 적용한 오프라인 전류모드제어 플라이백 변환기의 직류 바이어스 회로 해석 및 CTR 설계)

  • Lee, Seungjun;Kim, Hansang;Choi, Byungcho
    • Proceedings of the KIPE Conference
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    • 2015.07a
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    • pp.227-228
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    • 2015
  • 본 논문에서는 Optocoupler 절연형 오프라인 플라이백 변환기 궤환 단의 직류 바이어스 해석 기법을 제안한다. 직류 바이어스 해석을 통해 목표한 Current Transfer Ratio(CTR)를 얻고 Junction Capacitance($C_j$)를 측정하여 제어기 설계에 적용시켜 안정도 및 성능을 측정하였다. NCP1230, PC817, TL431 IC를 이용하여 플라이백 변환기의 제어회로를 제작하였고, 시뮬레이션을 이용해 직류 바이어스 해석 기법의 타당성을 검증하였다.

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A Study on the Structure of Polycrystalline Silicon Thin Film Transistor for Reducing Off-Current (OFF 전류의 감소를 위한 다결정 실리콘 박막 트랜지스터의 구조 연구)

  • Oh, Jeong-Min;Min, Byung-Hyuk;Han, Min-Koo
    • Proceedings of the KIEE Conference
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    • 1993.07b
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    • pp.1292-1294
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    • 1993
  • This paper proposes a new structure of polycrystalline silicon(poly-Si) thin film transistor(TFT) having a thick gate-oxide below the gate edge. The new structure is fabricated by the gate re-oxidation in wet ambient. It is shown that the thick gate-oxide below the gate edge is effective in reducing the leakage current and the gate-drain overlap capacitance. We have simulated this device by using the SSUPREM4 process simulator and the SPISCES-2B device simulator. As a simulation result it is found that the new structure provides a low tentage current less than 0.2 pA and achieves a on/off ratio as high as $5{\times}10^7$.

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