• Title/Summary/Keyword: capacitance ratio

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A Study on the Investigation of Performance for Evaluation Method of Unit Water Content of Fresh Concrete (굳지 않은 콘크리트 단위수량 추정기법의 성능 검토에 관한 연구)

  • Kim, Yong-Ro;Choi, Il-Ho;Jung, Yang-Hee;Kim, Hyo-Rak;Lee, Do-Bum
    • Proceedings of the Korea Concrete Institute Conference
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    • 2005.11a
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    • pp.367-370
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    • 2005
  • In this study, air meter method and capacitance measurement method to apply economically at quality control of ready-mixed concrete among various unit water content measurement technique was selected. Then, it was evaluated estimating performance of unit water content according to the change of water-binder ratio and unit water content. Also, it was examined influence about error occurrence of unit water content by change of properties of used materials. Finally, based on this study, it was proposed fundamental data to utilize measurement technique of unit water content to quality control. of ready-mixed concrete in construction field.

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Study of ZVS-PWM Series Resonant Converter with Active-Clamp Technique (액티브 클램프 기법을 이용한 영전압 스위칭 직렬 공진형 컨버터에 관한 연구)

  • Jeon, Hee-Cheol;Kim, Yong;Jung, Kye-Cheon;Kim, Pil-Soo;Lee, Eun-Young
    • Proceedings of the KIEE Conference
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    • 1999.07f
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    • pp.2674-2677
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    • 1999
  • Resonant converters have several salient features such as high efficiency and low noise. Therefore, ZVS-PWM controlled series resonant converter with active-clamp technique is presented. The combination of an active-clamp technique and resonant circuit makes it possible to control the output voltage of the resonant converter with PWM. This new resonant converter was implemented and has achieved a good controllability. In this paper, the normal load characteristics and abnormal voltage increase in the case of the light load are analyzed. As a result, it is clarified that the stray capacitance of the transformer is a cause of the abnormal voltage increase. Then, it is confirmed that the abnormal voltage increase is suppressed by decreasing the duty ratio. ZVS condition is analyzed. The maximum efficiency of 89% is obtained for the output of 10V and 5A.

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Influence of Substrate Temperature of SBN Ceramic Thin Film (SBN 세라믹 박막의 기판온도에 따른 영향)

  • Kim, Jin-Sa;Oh, Yong-Cheul;Shin, Cheol-Gi;Kim, Eung-Kwon;So, Byeong-Mun;Song, Min-Jong;Kim, Chung-Hyeok
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.11a
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    • pp.213-214
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    • 2008
  • The $Sr_{0.7}Bi_{2.3}Nb_2O_9$(SBN) thin films are deposited on Pt-coated electrode(Pt/Ti/SiO2/Si) using RF sputtering method at various substrate temperature. The optimum conditions of RF power and Ar/O2 ratio were 60[W] and 70/30, respectively. The crystallinity of SBN thin films were increased with increase of substrate temperature in the temperature range of 100~400[$^{\circ}C$]. The capacitance of SBN thin films were increased with the increase of substrate temperature.

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Theoretical Construction of a Floating-Mass (부동질량의 이론적 구성)

  • 이상배
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.16 no.1
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    • pp.22-25
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    • 1979
  • The mechanical floating-mass which is analogous to an electrical floating- capacitance may not come across because a mass element in a mechanical network must be attracted to rho ground which is the reference point. In this study the mechanical floating-mass is fonstructed by employing two simple support levers, one link, one mass, and four frictionless hearings. It also shows that the mechanical device can be used to give various equivalent masses by altering the arm ratio of the levers.

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An Inductive Micro Position Sensign System and Analysis of its Response Characteristics (인덕턴스형 미소 변위 측정 시스템과 응답 특성의 분석)

  • Choi, Dong-Jun;Choi, In-Mook;Kim, Soo-Hyun
    • Journal of the Korean Society for Precision Engineering
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    • v.18 no.3
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    • pp.189-194
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    • 2001
  • This paper presents a mew design of an inductive position sensing system with high sensitivity. The designed system consists of the driving coils, position-detecting coils, and closed loop formed magnetic blocks. To obtain high sensitivity we design a symmetric and closed loop type measuring system with small air-gaps. The elements that affect the system characteristics are turn ratio, excitation frequency, air-gap size, capacitance effect, and load resistance. By experimental investigation, the influences of these elements are examined and the system parameters are selected. The sensitivity of the newly designed system is greater than 2800mV/(V mm) and the linearity error is below${\pm}0.01%; in; the; range; of; {\pm}200{\mu}m$.

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Switch Level Logic Simulator Using Polynomial MOS Delay Model (다형식 MOS 지연시간 모델을 이용한 스윗치레벨 논리 시뮬레이터)

  • Jun, Young-Hyun;Jun, Ki;Park, Song-Bai
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.25 no.6
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    • pp.700-709
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    • 1988
  • A new technique is proposed for switch-level logic simulation for NMOS and CMOS logic circuits. For the simple inverter the rise or fall delay time is approximated by a product of polynomials of the input waveform slope, the output loading capacitance and the device configuration ratio, the polynomial coefficients being so determined as to best fit the SPICE simuladtion results for a given fabrication process. This approach can easily and accurately be extened to the case of multiple input transitions. The simulation results show that proposed method can predict the delay times within 5% error and with a speed up by a factor of three orders of magnitude for several circuits tested, as compared with the SPICE simulation.

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A Switch-Level CMOS Delay Time Modeling and Parameter Extraction (스위치 레벨 CMOS 지연시간 모델링과 파라미터 추출)

  • 김경호;이영근;이상헌;박송배
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.28A no.1
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    • pp.52-59
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    • 1991
  • An effective and accurate delay time model is the key problem in the simulation and timing verification of CMOS logic circuits. We propose a semi-analytic CMOW delay time model taking into account the configuration ratio, the input waveform slope and the load capacitance. This model is based on the Schichman Hodges's DC equations and derived on the optimally weighted switching peak current. The parameters necessary for the model calculation are automatically determined from the program. The proposed model is computationally effective and the error is typically within 10% of the SPICEA results. Compared to the table RC model, the accuracy is inproved over two times in average.

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Dielectric properties of (BaCa)(ZrTi)$_3$ ceramics for multilayer ceramic chip capacitor using Y5V (Y5V용 적층 칩 캐패시터를 위한 (BaCa)(ZrTi)$O_3$ 세라믹스 유전 특성)

  • Yoon, Jung-Rag;Lee, Serk-Won;Lee, Heun-Young
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2002.05c
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    • pp.75-78
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    • 2002
  • The dielectric properties for Ni electrode multilayer ceramic chip capacitor for Y5V has been studied with $(Ba_{0.93}Ca_{0.07})_m(Ti_{0.82}Zr_{0.18})O_2+MnO_2$ 0.2wt%, $Y_2O_3$ 0.18wt%, $SiO_2$ 0.15wt%, glass frit 1 wt% composition. The m ratio in the range of 1.006 ~ 1.012 have dielectric constant 9,500 ~ 14,500 and insulation resistance 390 ~ 460 $G{\Omega}$. Using the dielectrics, nikel electrode multilayer chip capacitor with Y5V, 104Z in EIA 0603 size specific capacitance were developed.

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Study on Electrical Characteristics of Chloromethylated Polyimide

  • Yu, I.H.;Zhong, Z-X;Lee, M.H.;Lee, S.H.
    • 한국정보디스플레이학회:학술대회논문집
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    • 2005.07a
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    • pp.472-475
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    • 2005
  • The electrical performances of liquid crystal (LC) cells with chloromethylated polyimide (CMPI) alignment layers were investigated. The CMPI layer was previously reported as a multifunctional layer that does role of LC alignment and planarization layer as well as photo-alignment material with high photosensitivity and excellent thermal stability. The capacitance-voltage (C-V) characteristics of LC cells with CMPI alignment layers were measured. Mechanical rubbing of the CMPI layer did not generate much difference in residual DC when compared to commercial PI. However, the LC cell with photo-oxidation CMPI layer shows a high residual DC value and a corresponding low voltage holding ratio (VHR) due to the photo-induced ionic charges on the alignment layer.

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Evaluation of Insulation Performance on Stator Windings of Inverter-Fed Induction Motor According to Impregnation Techniques (인버터 구동 유도전동기 고정자 권선의 함침기법에 따른 절연성능 평가)

  • Hwang, Don-Ha;Kang, Dong-Sik;Kim, Yong-Joo;Lee, In-Woo;Koo, Ja-Yoon;Kim, Dong-Hee;Lee, Kwang-Sik
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.55 no.7
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    • pp.373-379
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    • 2006
  • The low-voltage induction motors have been widely driven by IGBT PWM inverters, ever since it was used to apply variable speed drives. Recently, the insulation failures of the stator windings become critical problems due to the high ratio of dv/dt in IGBT PWM inverters. In this paper, the detailed insulation tests on the IGBT PWM inverter fed induction motor are carried out. Five different types of insulation techniques are used to ti induction motors. The change of the insulation characteristics such as partial discharge, AC current, capacitance, and dissipation factor are compared. respectively In addition, insulation breakdown tests using the high voltage pulse are performed, and corresponding breakdown voltages are analyzed.