• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.897-898
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• 2006

This paper proposes a new power-stage circuit that can be available for modularization of the power regulator which is used at the software-controlled unregulated bus system. And we analyze the proposed power-stage operation according to its operating modes and verify it by performing software simulation and hardware experiment using prototype. By constructing a parallel-module converter which is composed of proposed power-stages, we verify the operations and usefulness of the proposed power-stage.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.57 no.2
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• pp.109-114
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• 2008

In this paper, a dynamic learning controller for robot manipulator is implemented using real-time operating system with capabilities of multitasking, intertask communication and synchronization, event-driven, priority-driven scheduling, real-time clock control, etc. The controller hardware system with VME bus and related devices is developed and applied to implement a dynamic learning control scheme for robot manipulator. Real-time performance of the proposed dynamic learning controller is tested and evaluated for tracking of the desired trajectory and compared with the conventional servo controller.

• Proceedings of the KIEE Conference
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• 2003.07a
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• pp.221-223
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• 2003

In this paper, a sensitivity index is proposed for identifying the location of FACTS in the power system with PSS. The index can be calculated by using the bus impedance matrix of the power system. This index that is related with sensitivity matrix is included in the network and not in operating condition for power system. This index is applied to IEEE 9 bus test system.

• Proceedings of the KIEE Conference
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• 1993.07a
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• pp.134-136
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• 1993

This paper presents a novel and efficient method to calculate the critical point of voltage collapse. Conjugate gradient and modified Newton-Raphson methods are employed to calculate two pairs of multiple load flow solutions for two operating conditions, i.e., both +mode and -mode voltages for two loading conditions respectively. Then these four voltage magnitude-load data sets of the bus which is most susceptible to voltage collapse, are fitted to third order polynomial using Lagrangian interpolation in order to represent approximate nose curve (P-V curve). This nose curve locates first estimate of the critical point of voltage collapse. The procedure described above is repeated near the critical point and the new estimate will be very close to the critical point. The proposed method is tested for the eleven bus Klos-Kerner system, with good accuracy and fast computation time.

• Proceedings of the KIEE Conference
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• 2004.11b
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• pp.97-100
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• 2004

As the circumstance of the traditional system is changed according to power system deregulation, the simulation tool which should reflect market code providing market operating mechanism is needed to analyze an electricity market. This paper presents the development of Electricity Market Price Simulator for short term(EMPS) that is designed to imitate the Korean electricity market. The EMPS is developed in VB.NET and is composed if three functions that consist of calculating SMP for CBP market, MCP for TWBF market and LMP for LMP-market. To evidence the features and the performance of EMPS, a small two way bidding market with 12-bus system, one way bidding market for generator competition and LMP market with 5-bus system will be presented for the electricity market simulations using EMPS.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.959-961
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• 2003

In this paper, we describe implemented DMAC (Direct Memory Access Controller) architecture on Altera's $Excalibur^{TM}$ that includes industry-standard $ARM922T^{TM}$ 32-bit RISC processor core operating at 200 MHz. We implemented DMAC based on AMBA (Advanced Micro-controller Bus Architecture) AHB (Advanced Micro-performance Bus) interface. Implemented DMAC has 8-channel and can extend supportable channel count according to user application. We used round-robin method for priority selection. Implemented DMAC supports data transfer between Memory-to-Memory, Memory-to-Peripheral and Peripheral-to-Memory. The max transfer count is 1024 per a time and it can support byte, half-word and word transfer according to AHB protocol (HSIZE signals). We implemented with VHDL and functional verification using $ModelSim^{TM}$. Then, we synthesized using $LeonardoSpectrum^{TM}$ with Altera $Excalibur^{TM}$ library. We did FPGA P&R and targeting using $Quartus^{TM}$. We can use implemented DMAC module at any system that needs high speed and broad bandwidth data transfers.

• International journal of advanced smart convergence
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• v.12 no.4
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• pp.443-450
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• 2023

One of the basic tasks in the automobile manufacturing process is to design a bare chassis, which is the basic frame of a vehicle, and a bracket is a member connecting various devices to the frame. Bracket, which is a member connecting the engine, transmission, and suspension, which are the core devices of driving and operating the vehicle, to the frame, must maintain safety during vehicle operation. If the bracket connecting the various devices constituting the vehicle to the frame does not have durability, serious accidents may occur during operation of the vehicle. In this study, we performed stress analysis on the brackets installed in the bare chassis of the 25-passenger bus in the development stage. Based on the stress analysis performed, an improved bracket dimension was proposed.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.32 no.6D
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• pp.571-577
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• 2012

Recently, improving public transport service at disabled people has emerged as a social issue in rural areas. By improving expensive and inefficient existing operating system, the rural bus have to change a personalized service. Under these circumstances, government and local governments are promoting the introduction of DRT(Demand response transport). DRT system is intended to promote the user's convenience. But, until now, in-depth research on the operating costs for the introduction of DRT is not well known. This study aims to look at changes in number of vehicle and operating costs before and after introduction of DRT. The results are as follows. Even though introducing DRT, total number of vehicles increases because it does not reduce the existing number of vehicles. And this study estimated to about 5 to 12 percent of the increase in the operating cost comparing before introduction of DRT. Therefore, The introduction of DRT in rural areas is a need to set the exact purpose as promote transportation convenience or cost efficiency.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.33 no.3
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• pp.1115-1122
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• 2013

Recently the demands for traffic information tend to increase, and travel time might one of the most important traffic information. To effectively estimate exact travel time, highly reliable traffic data collection is required. BIS(Bus Information System) data would be useful for the estimation of the route travel time because BIS is collecting data for the bus travel time on the main road of the city on real-time basis. Traditionally use of BIS data has been limited to the realm of bus operating but it has not been used for a variety of traffic categories. Therefore, this study estimates a route travel time on road networks in urban areas on the basis of real-time data of BIS and then eventually constructs regression models. These models use an explanatory variable that corresponds to bus travel time excluding service time at the bus stop. The results show that the coefficient of determination for the constructed regression model is more than 0.950. As a result of T-test performance with assistance from collected data and estimated model values, it is likely that the model is statistically significant with a confidence level of 95%. It is generally found that the estimation for the exact travel time on real-time basis is plausible if the BIS data is used.

• International Journal of Highway Engineering
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• v.16 no.5
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• pp.99-108
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• 2014

PURPOSES : The travel times of expressway buses have been estimated using the travel time data between entrance tollgates and exit tollgates, which are produced by the Toll Collections System (TCS). However, the travel time data from TCS has a few critical problems. For example, the travel time data include the travel times of trucks as well as those of buses. Therefore, the travel time estimation of expressway buses using TCS data may be implicitly and explicitly incorrect. The goal of this study is to improve the accuracy of the expressway bus travel time estimation using DSRC-based travel time by identifying the appropriate analysis period of input data. METHODS : All expressway buses are equipped with the Hi-Pass transponders so that the travel times of only expressway buses can be extracted now using DSRC. Thus, this study analyzed the operational characteristics as well as travel time patterns of the expressway buses operating between Seoul and Dajeon. And then, this study determined the most appropriate analysis period of input data for the expressway bus travel time estimation model in order to improve the accuracy of the model. RESULTS : As a result of feasibility analysis according to the analysis period, overall MAPE values were found to be similar. However, the MAPE values of the cases using similar volume patterns outperformed other cases. CONCLUSIONS : The best input period was that of the case which uses the travel time pattern of the days whose total expressway traffic volumes are similar to that of one day before the day during which the travel times of expressway buses must be estimated.