• Journal of Korean Institute of Industrial Engineers
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• v.27 no.4
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• pp.406-412
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• 2001

IP address lookup is to determine the next hop destination of an incoming packet in the router. The address lookup is a major bottleneck in high performance router due to the increased routing table sizes, increased traffic, higher speed links, and the migration to 128 bits IPv6 addresses. IP lookup time is dependent on data structure of lookup table and search scheme. In this paper, we propose a new approach to build a lookup table that satisfies the memory constraint. The design of lookup table is formulated as an optimization problem. The objective is to minimize average depth from the root node for lookup. We assume that the frequencies with which prefixes are accessed are known and the data structure is level compressed trie with branching factor $\kappa$ at the root and binary at all other nodes. Thus, the problem is to determine the branching factor k at the root node such that the average depth is minimized. A heuristic procedure is proposed to solve the problem. Experimental results show that the lookup table based on the proposed heuristic has better average and the worst-case depth for lookup.

• Asian-Australasian Journal of Animal Sciences
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• v.33 no.2
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• pp.212-218
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• 2020

Objective: Agu pigs are indigenous to the Okinawa prefecture, which is the southernmost region of Japan. Agu pigs were exposed to a genetic bottleneck during the 20th century, due to the introduction of European pig breeds. The objective of this study was to elucidate the genetic structure of Agu pigs and to determine their relationships with those of five European breeds, two Chinese breeds and Ryukyu wild boar using microsatellite markers. Methods: A total of 203 DNA samples from 8 pig breeds were used in this study. Genotyping was performed using 21 microsatellite markers distributed across 17 chromosomes. Results: Numbers of effective alleles in Agu pigs were fewer than in European breeds and Ryukyu wild boar. Among domestic pigs, Agu pigs had the lowest heterozygosity (0.423) and highest inbreeding coefficient (F_IS = 0.202), indicating a severe loss of heterozygosity in Agu pigs possibly due to inbreeding. Neighbor-joining tree analysis was performed based on Reynolds' genetic distances, which clustered Agu pigs with Duroc pigs. However, principal component analysis revealed a unique genetic position of the Agu pig, and the second principal component separated Agu pigs from all other breeds. Structure analysis with the optimal assumption of seven groups (K = 7) indicated that Agu pigs form an independent cluster from the other breeds. In addition, high and significant F_ST values (0.235 to 0.413) were identified between Agu pigs and the other breeds. Conclusion: This study revealed a substantial loss of genetic diversity among Agu pigs due to inbreeding. Our data also suggest that Agu pigs have a distinctive genetic structure, although gene flows from European breeds were observed.

• The KIPS Transactions:PartA
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• v.10A no.5
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• pp.453-462
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• 2003

IP address lookup of router searches and decide proper output link using destination address of IP packet that arrie into router. The IP address lookup is essential part in te development of high-speed router needed to high-speed backbone network as one of bottleneck of router performance. This paper introduces DTC data structure that can support gigabit IP address lookup by dynamic trie compression technique that just uses small memory in conventional Pentium CPU. When make a forwarding table by trie compression, the DTC can dynamically select a size of data structure with considering correlation between table's size and searching speed. Also, when compress the prefix trie, DTC makes IP address lookup on the forwarding table of a search on the high speed SRAM cache by minimizing the size of data structure reflecting the structure of the trie. In the experiment result, the DTC data structure recorded performance of maximum $12.5{\times}10^5$ LPS (lookup per second) in conventional Pentium CPU through a dynamic building of most suitable compression over variety of routing tables.

• Journal of Broadcast Engineering
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• v.16 no.2
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• pp.258-273
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• 2011

This paper designs and implements a multi-view 3D video player system which is operated faster than existing video player systems. The structure for obtaining the near optimum speed in a multi-processor environment by parallelizing the component modules is proposed to process large volumes of multi-view image data at high speed. In order to use the concurrency of bottleneck, we designed image decoding, synthesis and rendering modules in a pipeline structure. For load balancing, the decoder module is divided into the unit of viewpoint, and the image synthesis module is geometrically divided based on synthesized images. As a result of this experiment, multi-view images were correctly synthesized and the 3D sense could be felt when watching the images on the multi-view autostereoscopic display. The proposed application processing structure could be used to process large volumes of multi-view image data at high speed, using the multi-processors to their maximum capacity.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.9
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• pp.1867-1879
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• 1997

DREAM-S is a distributed main-memory database system for the real-time processing of shared operational datra in ATM switching systems. DREAM-S has a client-server architecture in which only the server has the diskstorage, and provides the T-Tree index structure for efficient accesses to the data. We propose a recovery technique for the T-Tree index structre in DREAM-S. Although main-memory database system offer efficient access performance, the database int he main-memory may be broken when system failure such as database transaction failure or power failure occurs. Therfore, a recovery technique that recovers the database (including index structures) is essential for fault tolerant ATM switching systems. Proposed recovery technique relieves the bottleneck of the server processors disk operations by maintaining the T-Tree index structure only in the main-memory. In addition, fast recovery is guaranteed even in large number of client systems since the T-Tree index structure(s) in each system can be recovered cncurrently.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.12
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• pp.2340-2352
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• 1994

Under the current IN(Intelligent Network) Architecture, most of their function were performed in SSP(Service Switching point), so the provision or modification of service was limited. To over come these limitation, the structure of 'AIN(Advanced Intelligent Network)' emerged. In this paper, SSP for AIN structure is designed and its performance is evaluated. In other words, the requirements for AIN service implementation are specified on the basis of ITU-T Recommendations. From these requirments and TDX-10 Exchange architecture, the SSP for AIN structure is designed, and its performance is analyzed through the method of simulation and analytical modeling. As a conclusion of this paper, when the system is operated as a standard model, the maximum throughput is 1,270,000 BHCA for Free Phone Service and 1,190,000 BHCA for Credit Call Service. The processors in INS(Interconnection Network Subsystem) are proved to be bottleneck elements. To enhance the performance, several suggestions such as processor and link speedup, and other D_bus service policy are proposed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.7
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• pp.1018-1027
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• 1993

In this thesis, we evaluate the performance of the TDX-IB/ISDN Switching System ISS (ISDN Subscriber Subsystem) which is the ISDN user-network interface module. For this evaluation, performance indices are established and major performance parameters which influence message processing are extracted by studying the ISS structure and mechanism. To reflect these parameters, simulation model is developed and simulated. From the result of maximum throughput, message delay time, etc. , ISS message processing capability is evaluated and several method to enhance the system performance is proposed, by analyzing the system bottleneck element.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.11
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• pp.2313-2320
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• 2011

The management of a panel block shop in a shipyard is a complex process that entails the largest amount of work and in which many decisions are involved. Shipbuilders have considered the process as a bottleneck since every panel for every ship and offshore hull structure must be processed through the shop. In order to maximize process productivity, simulation-based ship production execution system(SPEXS) is proposed for panel block operations utilising discrete-event simulation and simulated annealing. An application of panel block assembly shop, called SPEX-Panel supports production planners by general dispatching rules and metaheuristics to make better scheduling decisions on the shop floor. In addition, the system will help increase productivity in the yard with continuous improvement.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.8
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• pp.732-744
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• 1991

In this paper, performance evaluation of the common channel signalling module which performs the message transfer part function of the CCITT No.7 in TDX 1 exchange is carried out. Simulation model is developed using SLAM II network nodes according to signalling mode and transrated into SLAM II statement, . The simulation results are compared with experimental results and analyzed in order to get the maximum throughput, processing delay time, bottleneck eiement. Also, in order to get the optimized structure of the CSM, simulation is performed on the vanous case, namely, change of the number of STB, change of STG bus or B bus speed, change of CSIOB, processing speed, change of the number of transfered message per one poll.

• IE interfaces
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• v.14 no.3
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• pp.247-254
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• 2001

As current postal automation is limited to dispatch and arrival sorting, delivery sequence sorting is performed manually by each postman. It not only acts as a bottleneck process in the overall mailing process but is expensive operation. To cope with this problem effectively, delivery sequence sorting automation is required. The important components of delivery sequence sorting automation system are sequence sorter and Hangul OCR which function is to extract the address of delivery point. DSI database will be interfaced to both Hangul OCR and sequence sorter for finding the accurate delivery sequence number and stacker number. The objectives of this research are to develop DSI(Delivery Sequence Information) database prototype and client application for managing information effectively. For database requirements collection and analysis, we draw all possible sorting plans, and apply the AHP(Analytic Hierarchy Process) method to determine the optimal one. And then, we design DSI database schema based on the optimal one and implement it using Oracle RDBMS. In addition, as address information in DIS database consist of hierarchical structure which has its correspondence sequence number, so it is important to reorganize sequence information accurately when address information is inserted, deleted or updated. To increase delivery accuracy, we reflect this point in writing application.