• KSII Transactions on Internet and Information Systems (TIIS)
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• v.15 no.5
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• pp.1728-1743
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• 2021

Three-dimensional (3D) video scenes are complex and difficult to control, especially when scene switching occurs. In this paper, we propose two algorithms based on an incremental proportional-integral-derivative (PID) algorithm and a similarity analysis between views to improve the method of bit allocation for multi-view high efficiency video coding (MV-HEVC). Firstly, an incremental PID algorithm is introduced to control the buffer "liquid level" to reduce the negative impact on the target bit allocation of the view layer and frame layer owing to the fluctuation of the buffer "liquid level". Then, using the image similarity between views is used to establish, a bit allocation calculation model for the multi-view video main viewpoint and non-main viewpoint is established. Then, a bit allocation calculation method based on hierarchical B frames is proposed. Experimental simulation results verify that the algorithm ensures a smooth transition of image quality while increasing the coding efficiency, and the PSNR increases by 0.03 to 0.82dB while not significantly increasing the calculation complexity.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.187-189
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• 2018

In this paper, the optimal design conditions for hardware implementation of the Secure Hash Algorithm3-512 (SHA3-512) hash function were analyzed. Five SHA3-512 hash cores with data-path of 64-bit, 320-bit, 640-bit, 960-bit, and 1600-bit were designed, and their functionality were verified by RTL simulation. Based on the results synthesized with Xilinx Virtex-5 FPGA device, we evaluated the performance of the SHA3-512 hash cores, including maximum frequency, throughput, and occupied slices. The analysis results show that the best hardware performance of SHA3-512 hash core can be achieved by designing it with 1600-bit data-path.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.5C
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• pp.498-504
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• 2009

A high-performance low-complexity decoding algorithm for LDPC codes is proposed in this paper, which has the advantages of both bit-flipping (BF) algorithm and sum-product algorithm (SPA). The proposed soft bit-flipping algorithm requires only simple comparison and addition operations for computing the messages between bit and check nodes, and the amount of those operations is also small. By increasing the utilization ratio of the computed messages and by adopting nonuniform quantization, the signal-to-noise ratio (SNR) gap to the SPA is reduced to 0.4dB at the frame error rate of 10-4 with only 5-bit assignment for quantization. LDPC codes with high column or row weights, which are not suitable for the SPA decoding due to the complexity, can be practically implemented without much worsening the error performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.6
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• pp.1471-1481
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• 1998

In this paper, we propose a new digital image stabilization scheme based on the bit-plane matching. In the proposed algorithm, the conventional motion estimation algorithms are applied to the binary images extracted from the bit-plane images. It is shown that the computational complexity of the proposed algorithm can be significantly reduced by replacing the arithmetic calculations with the binary Boolean functions, while the accuracy of motion estimation is maintained. Furthermore, an adaptive algorithm for selecting a bit-plane in consideration of changes in external illumination can provide the robustness of the proposed algorithm. We compared the proposed algorithm with existing algorithms using root mean square error (RMSE) on the basis of the brute-force method, and proved experimentally that the proposed method detects the camera motion more accurately than existing algorithms. In addition, the proposed algorithm performs digital image stabilization with less computation.

• Journal of information and communication convergence engineering
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• v.8 no.5
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• pp.539-543
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• 2010

We present a random bit generator that uses fingerprint image for the source of random, and random bit generator using fingerprint image for the randomness has not been presented as yet. Fingerprint image is affected by the operational environments including sensing act, nonuniform contact and inconsistent contact, and these operational environments make FPI to be used for the source of random possible. Our generator produces, on the average, 9,334 bits a fingerprint image in 0.03 second. We have used the NIST SDB14 test suite consisting of sixteen statistical tests for testing the randomness of the bit sequence generated by our generator, and as the result, the bit sequence passes all sixteen statistical tests.

• Journal of the Optical Society of Korea
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• v.12 no.3
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• pp.136-146
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• 2008

We proposed an adaptive steganography of an optical image using bit-planes and multichannel characteristics. The experiment's purpose was to compare the most popular methods used in optical steganography and to examine their advantages and disadvantages. In this paper we describe two digital methods: the first uses less significant bits(LSB) to encode hidden data, and in the other all blocks of $n{\times}n$ pixels are coded by using DCT(Digital Cosine Transformation), and two optical methods: double phase encoding and digital hologram watermarking with double binary phase encoding by using IFTA(Iterative Fourier Transform Algorithm) with phase quantization. Therefore, we investigated the complexity on bit plane and data, similarity insert information into bit planes. As a result, the proposed method increased the insertion capacity and improved the optical image quality as compared to fixing threshold and variable length method.

• Proceedings of the IEEK Conference
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• summer
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• pp.15-18
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• 2004

In this paper we present a linear discrete bit-loading algorithm that maximizes the transmit bit rate using the channel informations to optimize the performance of the very high-speed digital subscriber line(VDSL) system. It will be useful under the constraint of a maximum transmit power for each user. When the level of crosstalk is high, the power allocation of a user changes the noise experienced by the other users in the same binder. In this case, the performance of DSL modems can be improved by jointly considering the bit and power allocation of all users.

• Journal of Platform Technology
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• v.6 no.4
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• pp.26-33
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• 2018

In this paper, we propose an image retrieval algorithm for real-time processing and design it as hardware. The proposed method is based on the classification of BoWs(Bag of Words) algorithm and proposes an image search algorithm using bit stream. K-fold cross validation is used for the verification of the algorithm. Data is classified into seven classes, each class has seven images and a total of 49 images are tested. The test has two kinds of accuracy measurement and speed measurement. The accuracy of the image classification was 86.2% for the BoWs algorithm and 83.7% the proposed hardware-accelerated software implementation algorithm, and the BoWs algorithm was 2.5% higher. The image retrieval processing speed of BoWs is 7.89s and our algorithm is 1.55s. Our algorithm is 5.09 times faster than BoWs algorithm. The algorithm is largely divided into software and hardware parts. In the software structure, C-language is used. The Scale Invariant Feature Transform algorithm is used to extract feature points that are invariant to size and rotation from the image. Bit streams are generated from the extracted feature point. In the hardware architecture, the proposed image retrieval algorithm is written in Verilog HDL and designed and verified by FPGA and Design Compiler. The generated bit streams are stored, the clustering step is performed, and a searcher image databases or an input image databases are generated and matched. Using the proposed algorithm, we can improve convenience and satisfaction of the user in terms of speed if we search using database matching method which represents each object.

• Journal of the Korea Society of Computer and Information
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• v.13 no.5
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• pp.255-261
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• 2008

RFID(Radio Frequency IDentification) is a technology that automatically identifies objects containing the electronic tags by using radio frequency. In RFID system, the reader needs the anti collision algorithm for fast identifring all of the tags in the interrogation zone. This Paper proposes the tree based TPAE(Tag Prediction Algorithm using Extra bit) algorithm to arbitrate the tag collision. The proposed algorithm can identify tags without identifring all the bits in the tag ID. The reader uses the extra bit which is added to the tag ID and if there are two collided bits or multiple collided bits, it checks the extra bit and grasps the tag IDs concurrently. In the experiment, the proposed algorithm had about 50% less query iterations than query tree algorithm and binary search algorithm regardless of the number of tags and tag ID lengths.

• Journal of the Korea Society of Computer and Information
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• v.15 no.4
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• pp.27-36
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• 2010

The paper proposes RFB(Record Filtering using Bit-vector) join algorithm, an in-network strategy that uses bit-vector to drastically reduce the size of data and hence the communication cost. In addition, by eliminating data not involved in join result prior to actual join, communication cost can be minimized since not all data need to be moved to the join nodes. The simulation result shows that the proposed RFB algorithm significantly reduces the number of bytes to be moved to join nodes compared to the popular synopsis join(SNJ) algorithm.